Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.3.1. E-Tile Power Supply Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 14.  E-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCH_GXE[R1] Power Analog power, block level transmitter buffers for E-tile, specific to the right (R) side of the device.

Connect VCCH_GXE to a 1.1-V low noise switching regulator.

VCCH_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCRT_GXE[R1] Power Analog power, used for the high-speed circuitry for the E-tile, specific to the right (R) side of the device.

VCCRT_GXE can be connected to a 0.9-V low noise switching regulator.

You must connect VCCRT_GXE to VCCH through an LC filter. For more information about the LC filter design, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCRT_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCRTPLL_GXE[R1] Power Analog power, used for the high-speed circuitry for the E-tile, specific to the right (R) side of the device.

You must source the VCCRTPLL_GXE from the VCCH with proper isolation filtering.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel® Agilex™ Power Management User Guide.

VCCRTPLL_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCCLK_GXE[R1] Power I/O power, specific to the E-tile reference clock buffers.

Connect VCCCLK_GXE to a 2.5-V low noise switching regulator.

VCCCLK_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCC_HSSI_GXE[R1] Power Primary digital supply for all digital signals, specific to E-tile.

Connect VCC_HSSI_GXE to a 0.9-V low noise switching regulator. This voltage rail must be shared with VCCH.

VCC_HSSI_GXE must be powered up even when the E-tile transceivers are not used.

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