Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.2.3. Optional/Dual-Purpose Configuration Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Attention: There are pins usage restriction for the dual-purpose pins in the Avalon® -ST x16 and x32 modes. For more information, refer to section 2.5.3.2. Enabling Dual-Purpose Pins in the Intel® Agilex™ Configuration User Guide.
Table 4.  Optional/Dual-Purpose Configuration Pins
Pin Name Pin Functions Pin Description Connection Guidelines
AVST_DATA[31:0] I/O, Input

Dual-purpose configuration data input pins.

Use AVST_DATA[15:0] pins for Avalon® Streaming Interface ( Avalon® -ST) x16 mode, AVST_DATA [31:0] pins for Avalon® -ST x32 mode, or as regular I/O pins.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Attention: Access to the I/O pins located in bank 3A with pin index[91...95] is not allowed for the AvSTx16 or AvSTx32 configuration scheme. You must leave these pins unconnected. For more information, refer to the device pin mapping files to identify the exact pin location.
If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected.
AVST_READY(3A bank) I/O, Output

Dual-purpose Avalon® -ST interface data ready output pin. This pin is used for the Avalon® -ST x16 and x32 configuration schemes.

This pin cannot be used as a user I/O pin if you are using the AvST x16 or AvST x32 configuration scheme.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Connect this pin to the ready signal input of the external configuration controller when configuring using the Avalon® -ST x16 or x32 interface.
AVST_CLK(3A bank) I/O, Input

Dual-purpose Avalon® -ST interface clock input pin. This pin is used for the Avalon® -ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Connect this pin to the clock signal of the external configuration controller when configuring using the Avalon® -ST x16 or x32 interface.

Connect unused pins as defined in the Intel® Quartus® Prime software.

AVST_VALID(3A bank) I/O, Input

Dual-purpose configuration data valid pin. This pin is used for the Avalon® -ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Connect this pin to the data valid signal of the external configuration controller when configuring using the Avalon® -ST x16 or x32 interface.

Connect unused pins as defined in the Intel® Quartus® Prime software.

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