Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
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1.7.4. HPS GPIO Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 25.  HPS GPIO PinsThere are two GPIO controllers (GPIO0 and GPIO1) for the Intel® Agilex™ HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
GPIO0_IO[0..23]

General purpose input output.

Ensure that the I/O standard used is compatible with VCCIO_HPS.

I/O

HPS_IOA_[1..24]

HPS_IOB_[1..24]

GPIO1_IO[0..23]

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