Visible to Intel only — GUID: vrz1552555104633
Ixiasoft
Visible to Intel only — GUID: vrz1552555104633
Ixiasoft
1.7.3. HPS JTAG Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
JTAG_TCK | HPS JTAG test clock input pin. Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. If you do not intend to utilize the HPS, you cannot use the HPS_IOA/B pins. |
Input | HPS_IOB_9 |
JTAG_TMS | HPS JTAG test mode select input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. If you do not intend to utilize the HPS, you cannot use the HPS_IOA/B pins. |
Input | HPS_IOB_10 |
JTAG_TDO | HPS JTAG test data output pin. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. If you do not intend to utilize the HPS, you cannot use the HPS_IOA/B pins. |
Output | HPS_IOB_11 |
JTAG_TDI | HPS JTAG test data input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. If you do not intend to utilize the HPS, you cannot use the HPS_IOA/B pins. |
Input | HPS_IOB_12 |