Intel® Agilex™ Device Family Pin Connection Guidelines

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ID 683112
Date 6/21/2022
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1.7.3. HPS JTAG Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 24.  HPS JTAG PinsYou have the option to connect HPS JTAG pins to the HPS Dedicated I/O using the following assignments.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
JTAG_TCK

HPS JTAG test clock input pin.

Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

Input HPS_IOB_9
JTAG_TMS

HPS JTAG test mode select input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

Input HPS_IOB_10
JTAG_TDO

HPS JTAG test data output pin.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

Output HPS_IOB_11
JTAG_TDI

HPS JTAG test data input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

Input HPS_IOB_12

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