Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.2.5. External Memory Interface Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 6.  External Memory Interface Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DQS[0:63] I/O, bidirectional

Optional data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

  • POD 1.2-V I/O standard
  • SSTL 1.2-V I/O standard
Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[0:63] I/O, bidirectional

Optional complementary data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

  • POD 1.2-V I/O standard
  • SSTL 1.2-V I/O standard
Connect unused pins as defined in the Intel® Quartus® Prime software.
DQ[0:63] I/O, bidirectional

Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the device pin-out file.

Supported I/O standards:

  • POD 1.2-V I/O standard
  • SSTL 1.2-V I/O standard
Connect unused pins as defined in the Intel® Quartus® Prime software.

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