1.6.2. R-Tile Transceiver Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
GXR_RCOMP_P_0 | Input | External biasing resistor for R-tile. | Connect a 150-ohm 1% resistor between the GXR_RCOMP_N_0 pin and GXR_RCOMP_P_0 pin of each R-tile bank. RCOMP_P + RCOMP_N total trace routing (package and board) resistance is less than 0.500 ohms. In the PCB layout, do not route traces next to high speed clock/data aggressors. You are required to keep the maximum capacitance on RCOMP_P less than 5.0 pF. If this tile is unused, leave these pins floating. |
GXR_RCOMP_N_0 | |||
I_PIN_PERST_N_GXR | Input | PCI Express* ( PCIe* ) Platform reset pin. | In a PCIe adapter card implementation, connect the PCIe nPERST signal from the PCIe edge connector to each R-tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe connector to the 1.0-V I_PIN_PERST_N input of each R-tile transceiver that is used on the board. Provide a 1.0-V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe connector is an open-drain signal. You must pull up the 3.3-V PCIe nPERST signal on the adapter card. If the tile is unused, tie to GND. In cases where two independent clock sources are used for 2x8 bifurcation mode, ensure that I_PIN_PERST_N is de-asserted high after both reference clocks are stable. |
REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]P | Input | Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device. For more information about the supported pins, refer to the device pin-out file. |
It supports HCSL I/O standard only, must be DC coupled. You must connect a 100-MHz +/-100ppm reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ± 100ppm requirement for Gen 5. For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources. Leave these pins floating if unused. |
REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]N | |||
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]P | Input | Transceiver receiver pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device. For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps. For more information about the supported pins, refer to the device pin-out file. |
Leave these pins floating if unused. |
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]N | |||
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]P | Output | Transceiver transmitter pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device. For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps. For more information about the supported pins, refer to the device pin-out file. |
Transmitter pins must be AC coupled. Leave these pins floating if unused. |
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]N |
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