Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.6.2. Agilex™ 7 R-Tile Transceiver Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 21.   Agilex™ 7 R-Tile Transceiver PinsFor more information, refer to the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide .
Pin Name Pin Functions Pin Description Connection Guidelines
IO_RCOMP_0_P_GXR Input External biasing resistor for R-Tile.

Connect a 150 Ω 1% resistor between the IO_RCOMP_0_N_GXR pin and IO_RCOMP_0_P_GXR pin of each R-Tile bank.

RCOMP_P and RCOMP_N total trace routing (package and board) resistance is less than 0.500 Ω.

In the PCB layout, do not route traces next to high-speed clock or data aggressors. You are required to keep the maximum capacitance on RCOMP_P less than 5.0 pF.

IO_ROMP_1_P and IO_ROMP_1_N are only available on the Agilex™ 7 AGI041 device.

If this tile is unused, leave these pins floating.
IO_RCOMP_0_N_GXR
IO_RCOMP_1_P_GXR Input

External biasing resistor for R-Tile.
IO_RCOMP_1_N_GXR
I_PIN_PERST_N_GXR Input PCI Express* ( PCIe* ) Platform reset pin.

The usage of this pin is different between the Agilex™ 7 AGI041 device and other Agilex™ 7 FPGA devices.

For Agilex™ 7 I-series devices except for the Agilex™ 7 AGI041 device:

  • In a PCIe* adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each R-Tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.
  • In 2 x 8 bifurcation EP mode, in cases where two independent clock sources are used for 2 x 8 bifurcation mode, ensure that the I_PIN_PERST_N is de-asserted high after both REFCLK_GXR_CH0 and REFCLK_GXR_CH1 are stable.

For Agilex™ 7 AGI041 device:

  • In 1 x 16 root port (RP), 1 x 16 TLP bypass mode (BP), 1 x 16 end point (EP), 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, connect the PCIe* nPERST signal from the PCIe* edge connector to each R-Tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.
  • In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), this I_PIN_PERST_N pin must be de-asserted high after REFCLK_GXR_CH2 is stable for at least 100 µs.

If the tile is unused for both Agilex™ 7 AGI041 and other Agilex™ 7 devices, tie to GND.

I_PIN_PERST[0,1]_N_GXR Input

PCI Express* ( PCIe* ) PORT0 and PORT1 reset pin.

Active low. These two pins are only available in the Agilex™ 7 AGI041 device.

  • In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, leave these two pins floating, or pull up to VCCCLK_GXR through a resistor respectively, or tie them to GND.
  • In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), I_PIN_PERST0_N is the independent reset signal for PORT0 and I_PIN_PERST1_N is the independent reset signal for PORT1. In a PCIe* adapter card implementation with 2 x 8 EP mode, connect the PCIe* nPERST signal from the PCIe* edge connector to the corresponding I_PIN_PERST0_N or I_PIN_PERST1_N signal. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST0_N or I_PIN_PERST1_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST0_N or I_PIN_PERST1_N input if the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card. In cases where two independent clock sources are used, ensure that I_PIN_PERST0_N is de-asserted high after REFCLK_GXR_CH0 is stable and I_PIN_PERST1_N is de-asserted high after REFCLK_GXR_CH1 is stable. If any port is unused, its corresponding I_PIN_PERST_N pin must be tied to GND.
REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]P Input

Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For more information about the supported pins, refer to the device pin-out file.

It supports HCSL I/O standard only, must be DC coupled.

For all Agilex™ 7 I-series devices, including the Agilex™ 7 AGI041 device:

  • In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, you must connect a 100 MHz ±100 ppm reference clock to both reference clock inputs. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ±100 ppm requirement for Gen 5.
  • In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

Leave these pins floating if unused.
REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]N
REFCLK_GXR[R,L] [14A,14C,15C]_CH2P Input

Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the FPGA core fabric.

For more information about the supported pins, refer to the device pin-out file.

These two pins are only available in the Agilex™ 7 AGI041 device.

It supports HCSL I/O standard only, must be DC coupled.

  • In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, this reference clock can be tied to GND or connect a 100 MHz ±100 ppm local board reference clock to this reference clock input.
  • In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), you must connect a 100 MHz ±100 ppm local board reference clock to the reference clock input to ensure this reference clock is always provided.
    Note: This pin does not require a specific Quartus Setting File assignment for its pin location. You must not make a specific location assignment for this pin because the Quartus® Prime tool selects the corresponding pin location based on the location assignments made for the rest of the R-Tile pins.

Leave these pins floating if unused.
REFCLK_GXR[R,L] [14A,14C,15C]_CH2N
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]P Input

Transceiver receiver pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

 Leave these pins floating if unused.
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]N
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]P Output

Transceiver transmitter pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

Transmitter pins must be AC coupled.

Leave these pins floating if unused.
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]N
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