Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
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Document Table of Contents
Document Table of Contents
1. Intel® Agilex™ Device Family Pin Connection Guidelines
1. Intel® Agilex™ Device Family Pin Connection Guidelines
1.1. Pins Status for Intel® Agilex™ Devices 1.2. Intel® Agilex™ FPGA Core Pins 1.3. Intel® Agilex™ E-Tile Pins 1.4. Intel® Agilex™ P-Tile Pins 1.5. Intel® Agilex™ F-Tile Pins 1.6. Intel® Agilex™ R-Tile Pins 1.7. Intel® Agilex™ Hard Processor System (HPS) Pins 1.8. Intel® Agilex™ Power Supply Sharing Guidelines 1.9. Notes to Intel® Agilex™ Device Family Pin Connection Guidelines 1.10. Document Revision History for the Intel® Agilex™ Device Family Pin Connection Guidelines
1.2. Intel® Agilex™ FPGA Core Pins
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Intel® Agilex™ E-Tile Pins
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Intel® Agilex™ P-Tile Pins
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Intel® Agilex™ F-Tile Pins
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Intel® Agilex™ R-Tile Pins
1.6.1. R-Tile Power Supply Pins 1.6.2. R-Tile Transceiver Pins
1.7. Intel® Agilex™ Hard Processor System (HPS) Pins
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Intel® Agilex™ Power Supply Sharing Guidelines
1.8.1. Example 1— Intel® Agilex™ Devices (P-Tile and E-Tile) 1.8.2. Example 2— Intel® Agilex™ Devices (F-Tile and R-Tile)
1. Intel® Agilex™ Device Family Pin Connection Guidelines

1.6.2. R-Tile Transceiver Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 21.  R-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
GXR_RCOMP_P_0 Input External biasing resistor for R-tile.

Connect a 150-ohm 1% resistor between the GXR_RCOMP_N_0 pin and GXR_RCOMP_P_0 pin of each R-tile bank.

RCOMP_P + RCOMP_N total trace routing (package and board) resistance is less than 0.500 ohms.

In the PCB layout, do not route traces next to high speed clock/data aggressors. You are required to keep the maximum capacitance on RCOMP_P less than 5.0 pF.

If this tile is unused, leave these pins floating.
GXR_RCOMP_N_0
I_PIN_PERST_N_GXR Input PCI Express* ( PCIe* ) Platform reset pin.

In a PCIe adapter card implementation, connect the PCIe nPERST signal from the PCIe edge connector to each R-tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe connector to the 1.0-V I_PIN_PERST_N input of each R-tile transceiver that is used on the board.

Provide a 1.0-V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe connector is an open-drain signal. You must pull up the 3.3-V PCIe nPERST signal on the adapter card.

If the tile is unused, tie to GND.

In cases where two independent clock sources are used for 2x8 bifurcation mode, ensure that I_PIN_PERST_N is de-asserted high after both reference clocks are stable.

REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]P Input

Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device.

For more information about the supported pins, refer to the device pin-out file.

It supports HCSL I/O standard only, must be DC coupled.

You must connect a 100-MHz +/-100ppm reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ± 100ppm requirement for Gen 5.

For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

Leave these pins floating if unused.
REFCLK_GXR[R,L][14A,14C,15A,15C]_CH[0,1]N
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]P Input

Transceiver receiver pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

 Leave these pins floating if unused.
GXR[R,L][14A,14C,15A,15C]_RX_CH[0:15]N
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]P Output

Transceiver transmitter pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

Transmitter pins must be AC coupled.

Leave these pins floating if unused.
GXR[R,L][14A,14C,15A,15C]_TX_CH[0:15]N
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