Connect a 150 Ω 1% resistor between the IO_RCOMP_0_N_GXR pin and IO_RCOMP_0_P_GXR pin of each R-Tile bank.

RCOMP_P and RCOMP_N total trace routing (package and board) resistance is less than 0.500 Ω.

In the PCB layout, do not route traces next to high-speed clock or data aggressors. You are required to keep the maximum capacitance on RCOMP_P less than 5.0 pF.

IO_ROMP_1_P and IO_ROMP_1_N are only available on the Agilex™ 7 AGI041 device.

If this tile is unused, leave these pins floating.

External biasing resistor for R-Tile.

The usage of this pin is different between the Agilex™ 7 AGI041 device and other Agilex™ 7 FPGA devices.

For Agilex™ 7 I-series devices except for the Agilex™ 7 AGI041 device:

• In a PCIe* adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each R-Tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.
• In 2 x 8 bifurcation EP mode, in cases where two independent clock sources are used for 2 x 8 bifurcation mode, ensure that the I_PIN_PERST_N is de-asserted high after both REFCLK_GXR_CH0 and REFCLK_GXR_CH1 are stable.

For Agilex™ 7 AGI041 device:

• In 1 x 16 root port (RP), 1 x 16 TLP bypass mode (BP), 1 x 16 end point (EP), 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, connect the PCIe* nPERST signal from the PCIe* edge connector to each R-Tile transceiver bank I_PIN_PERST_N input. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.
• In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), this I_PIN_PERST_N pin must be de-asserted high after REFCLK_GXR_CH2 is stable for at least 100 µs.

If the tile is unused for both Agilex™ 7 AGI041 and other Agilex™ 7 devices, tie to GND.

PCI Express* ( PCIe* ) PORT0 and PORT1 reset pin.

Active low. These two pins are only available in the Agilex™ 7 AGI041 device.

• In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, leave these two pins floating, or pull up to VCCCLK_GXR through a resistor respectively, or tie them to GND.
• In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), I_PIN_PERST0_N is the independent reset signal for PORT0 and I_PIN_PERST1_N is the independent reset signal for PORT1. In a PCIe* adapter card implementation with 2 x 8 EP mode, connect the PCIe* nPERST signal from the PCIe* edge connector to the corresponding I_PIN_PERST0_N or I_PIN_PERST1_N signal. Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.0 V I_PIN_PERST0_N or I_PIN_PERST1_N input of each R-Tile transceiver that is used on the board. Provide a 1.0 V pull-up resistor to the I_PIN_PERST0_N or I_PIN_PERST1_N input if the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card. In cases where two independent clock sources are used, ensure that I_PIN_PERST0_N is de-asserted high after REFCLK_GXR_CH0 is stable and I_PIN_PERST1_N is de-asserted high after REFCLK_GXR_CH1 is stable. If any port is unused, its corresponding I_PIN_PERST_N pin must be tied to GND.

Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For more information about the supported pins, refer to the device pin-out file.

It supports HCSL I/O standard only, must be DC coupled.

For all Agilex™ 7 I-series devices, including the Agilex™ 7 AGI041 device:

• In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, you must connect a 100 MHz ±100 ppm reference clock to both reference clock inputs. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ±100 ppm requirement for Gen 5.
• In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

Leave these pins floating if unused.

Standard PCIe* High Speed Current Steering Logic (HCSL) reference clock input pins, specific to the FPGA core fabric.

For more information about the supported pins, refer to the device pin-out file.

These two pins are only available in the Agilex™ 7 AGI041 device.

It supports HCSL I/O standard only, must be DC coupled.

• In 1 x 16 RP, 1 x 16 BP, 1 x 16 EP, 2 x 8 RP, 2 x 8 BP, 2 x 8 EP (with the Enable Independent PERST pins parameter set to disable in the Quartus® Prime IP), 4 x 4 RP, 4 x 4 BP, and 4 x 4 EP, this reference clock can be tied to GND or connect a 100 MHz ±100 ppm local board reference clock to this reference clock input.
• In 2 x 8 EP (with the Enable Independent PERST pins parameter set to enable in the Quartus® Prime IP), you must connect a 100 MHz ±100 ppm local board reference clock to the reference clock input to ensure this reference clock is always provided.
  Note: This pin does not require a specific Quartus Setting File assignment for its pin location. You must not make a specific location assignment for this pin because the Quartus® Prime tool selects the corresponding pin location based on the location assignments made for the rest of the R-Tile pins.

Leave these pins floating if unused.

Transceiver receiver pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

Transceiver transmitter pins, specific to the R-Tile transceivers on the left (L) side or right (R) side of the device.

For PCIe* Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

For more information about the supported pins, refer to the device pin-out file.

Transmitter pins must be AC coupled.

Leave these pins floating if unused.