Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.2.8. Reference Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 9.  Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines

RZQ_[T,B]_2[A,B,C,D,E,F]

RZQ_[T,B]_3[A,B,C,D,E,F]

I/O, bidirectional

Reference pins for I/O banks. The RZQ pins share the same VCCIO_PIO with the I/O bank where they are located.

Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

These pins support 1.2-V I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

For more information about the supported pins, refer to the device pin-out file.

When using OCT, tie these pins to GND through a 240-Ω resistor.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected.

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