Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.7.5. HPS SDMMC Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 26.  HPS SDMMC Pins Intel® recommends adding a 1-kΩ to 10-kΩ pull-up resistor to every SDMMC data signal that is used.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2
SDMMC_CCLK SDMMC clock out Output HPS_IOA_1 HPS_IOB_15
SDMMC_CMD

SDMMC command line.

Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS.

I/O HPS_IOA_2 HPS_IOB_14
SDMMC_DATA0 SDMMC Data 0 I/O HPS_IOA_3 HPS_IOB_13
SDMMC_DATA1 SDMMC Data 1 I/O HPS_IOA_4 HPS_IOB_16
SDMMC_DATA2 SDMMC Data 2 I/O HPS_IOA_5 HPS_IOB_17
SDMMC_DATA3

SDMMC Data 3

When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash.

I/O HPS_IOA_6 HPS_IOB_18
SDMMC_DATA4 SDMMC Data 4 I/O HPS_IOA_7 HPS_IOB_19
SDMMC_DATA5 SDMMC Data 5 I/O HPS_IOA_8 HPS_IOB_20
SDMMC_DATA6 SDMMC Data 6 I/O HPS_IOA_9 HPS_IOB_21
SDMMC_DATA7 SDMMC Data 7 I/O HPS_IOA_10 HPS_IOB_22
SDMMC_PWR_EN SDMMC Power Enable Output HPS_IOA_11 HPS_IOB_23

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