Intel® Agilex™ Device Family Pin Connection Guidelines

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ID 683112
Date 6/21/2022
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1.4.1. P-Tile Power Supply Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 16.  P-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCH_GXP[L1,L3] Power

Secondary high-voltage analog supply for transceivers, and on-die PLL specific to P-tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCH_GXP to a 1.8-V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

VCCH_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCRT_GXP[L1,L3] Power

Primary analog supply for the TX and RX channels, specific to P-tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCRT_GXP to a 0.9-V low noise switching regulator. This voltage rail can be shared with VCCH using proper isolation filtering.

VCCRT_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCCLK_GXP[L1,L3] Power

LVCMOS I/O buffer supply rail, specific to P-tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCCLK_GXP to a 1.8V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

VCCCLK_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCCFUSE_GXP Power

Required power supply for the firmware to read internal settings for the one-time programmable eFuses.

Connect this voltage rail to a 0.9-V power supply. This rail must be shared with VCC_HSSI_GXP.

VCCFUSE_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

VCC_HSSI_GXP[L1,L3] Power

Primary digital supply for all digital signals, specific to P-tile.

For more information about the supported pins, refer to the device pin-out file.

Connect VCC_HSSI_GXP to a 0.9-V low noise switching regulator. This voltage rail must be shared with VCCH.

VCC_HSSI_GXP must be powered up even when the P-tile transceivers are not used.

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