Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
Public
Download
Document Table of Contents

1.7.10. HPS I2C Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

In addition to the three I2C_EMAC controllers, there are two additional I2C controllers (I2C0 and I2C1) for dedicated I2C usage in the Intel® Agilex™ HPS.

The I2C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading, but it is typically 4.7-kΩ or lower.

Table 31.  HPS I2C Pins
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2 Group 3 Group 4
I2C0 _SDA I2C0 Serial Data I/O HPS_IOA_5 HPS_IOA_23 HPS_IOB_3
I2C0 _SCL I2C0 Serial Clock I/O HPS_IOA_6 HPS_IOA_24 HPS_IOB_4
I2C1 _SDA I2C1 Serial Data I/O HPS_IOA_3 HPS_IOA_21 HPS_IOB_7 HPS_IOB_13
I2C1 _SCL I2C1 Serial Clock I/O HPS_IOA_4 HPS_IOA_22 HPS_IOB_8 HPS_IOB_14

Did you find the information on this page useful?

Characters remaining:

Feedback Message