Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile)

Table 35.  Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile TransceiversExample Requiring 8 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1 SmartVID1, 0.8 ± 3% Switcher 2 Share

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

For -4X devices, VCC and VCCP are powered by SmartVID and a separate fixed 0.8 V supply must be used for VCCL_HPS and filtered VCCPLLDIG_HPS.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to these power supply pins. Do not leave the VCCL_HPS and VCCPLLDIG_HPS power supply pins floating or connected to GND.

VCCP Share
VCCL_HPS Share
VCCPLLDIG_HPS Filter
VCCH 2 0.9 ± 30 mV Switcher2 Share

Connect the VCCH to a dedicated 0.9-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCC_HSSI_GXE Share
VCCFUSE_GXP Share
VCC_HSSI_GXP[L] Share
VCCH_SDM Share
VCCRT_GXE LC Filter
VCCRTPLL_GXE Filter
VCCRT_GXP Filter
VCCL_SDM 3 0.8 ± 3% Switcher2 Share

Connect the VCCL_SDM to a dedicated 0.8-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCPLLDIG_SDM Filter
VCCH_GXE 4 1.1 ± 3% Switcher2 Isolate

Connect the VCCH_GXE to a dedicated 1.1-V power supply.

VCCCLK_GXE 5 2.5 ± 5% Switcher2 Isolate

Connect the VCCCLK_GXE to a dedicated 2.5-V power supply.

VCCPT 6 1.8 ± 3% Switcher2 Share

Connect VCCPT to a dedicated 1.8-V power supply. Connect VCCADC, VCCPLL_SDM, VCCPLL_HPS, and VCCCLK_GXP to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Agilex™ 7 devices. If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to the HPS power supply pins.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCADC Filter
VCCPLL_SDM
VCCPLL_HPS
VCCCLK_GXP Filter
VCCH_GXP Filter
VCCRCORE 7 1.2 ± 5% Switcher2 Share

Connect the VCCRCORE to 1.2-V power supply.

Connect VCCIO_PIO and VCCIO_PIO_SDM to dedicated 1.2-V power supply.

Connect VCCA_PLL to the VCCRCORE, VCCIO_PIO, and VCCIO_PIO_SDM supplies with proper isolation filtering.

VCCIO_PIO 3
VCCIO_PIO_SDM
VCCA_PLL Filter
VCCIO_SDM 8 1.8 ± 5% Switcher2 Share Connect VCCIO_SDM and VCCIO_HPS to dedicated 1.8-V power supply.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to these power supply pins. Do not leave the VCCIO_HPS power supply pins floating or connected to GND.

VCCIO_HPS Share
VCCFUSEWR_SDM Share

A 1.8-V power supply is required on this pin if field-programming of the eFuses is required. In addition, Intel recommends connecting a regulator with 1.8-V output to allow access to enhanced configuration and security debug tools. If you choose not to power this pin, tie this pin to VCCIO_SDM or leave it unconnected (floating). Do not tie this pin to GND.

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Agilex™ 7 device is provided in the Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers figure.

Figure 1. Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers
Related Information
1 For the SmartVID voltage range, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .
2 When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 4 of the Notes to Agilex™ 7 Pin Connection Guidelines.
3 The supported tolerance for the VCCIO_PIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . Use the Intel® FPGA Power and Thermal Calculator and the Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
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