Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
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Document Table of Contents
Document Table of Contents
1. Intel® Agilex™ Device Family Pin Connection Guidelines
1. Intel® Agilex™ Device Family Pin Connection Guidelines
1.1. Pins Status for Intel® Agilex™ Devices 1.2. Intel® Agilex™ FPGA Core Pins 1.3. Intel® Agilex™ E-Tile Pins 1.4. Intel® Agilex™ P-Tile Pins 1.5. Intel® Agilex™ F-Tile Pins 1.6. Intel® Agilex™ R-Tile Pins 1.7. Intel® Agilex™ Hard Processor System (HPS) Pins 1.8. Intel® Agilex™ Power Supply Sharing Guidelines 1.9. Notes to Intel® Agilex™ Device Family Pin Connection Guidelines 1.10. Document Revision History for the Intel® Agilex™ Device Family Pin Connection Guidelines
1.2. Intel® Agilex™ FPGA Core Pins
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Intel® Agilex™ E-Tile Pins
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Intel® Agilex™ P-Tile Pins
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Intel® Agilex™ F-Tile Pins
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Intel® Agilex™ R-Tile Pins
1.6.1. R-Tile Power Supply Pins 1.6.2. R-Tile Transceiver Pins
1.7. Intel® Agilex™ Hard Processor System (HPS) Pins
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Intel® Agilex™ Power Supply Sharing Guidelines
1.8.1. Example 1— Intel® Agilex™ Devices (P-Tile and E-Tile) 1.8.2. Example 2— Intel® Agilex™ Devices (F-Tile and R-Tile)
1. Intel® Agilex™ Device Family Pin Connection Guidelines

1.3.2. E-Tile Transceiver Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 15.  E-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines

GXE[R9A]_RX_CH[0:23][p,n]

Input

High speed differential serial inputs to receiver circuitry. Specific to the E-tile transceiver on the right (R) side of the device.

Supports both NRZ and PAM4 modulation. For the supported data rates, refer to the Intel® Agilex™ Device Data Sheet.

No off-chip AC-coupling capacitor is required if the RX input common mode is between VCCRT_GXE and GND, and the RX input amplitude difference is less than 1200 mVp-p. The absolute maximum input to the E-Tile SerDes is VCCRT_GXE + 300 mV to prevent forward biasing of the ESD diodes.

When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. For more information about the external AC-coupling, refer to the E-Tile Transceiver PHY User Guide.

Leave unused pins floating.
GXE[R9A]_TX_CH[0:23][p,n] Output

High speed differential serial outputs from the transmitter circuitry. Specific to the E-tile transceiver on the right (R) side of the device.

Supports both NRZ and PAM4 modulation. For the supported data rates, refer to the Intel® Agilex™ Device Data Sheet.

Leave unused pins floating.
REFCLK_GXE[R9A]_CH[0:8][p,n] Input

High speed differential reference clock connects to the E-tile transceiver of the right (R) side of the device.

REFCLK_GXE is supplied to both RX and TX independently.

REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode.

Supported I/O standard:

  • LVPECL

The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination. You have to enable the internal terminations in the Intel® Quartus® Prime software.

Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to the Reference Clock Pins section of the E-Tile Transceiver PHY User Guide.

Tie each unused REFCLK pin to GND through a 1-kΩ resistor.

REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to the Dynamic Reconfiguration Flow for Special Cases section of the E-Tile Transceiver PHY User Guide.

Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to the Unused Transceiver Channels section of the E-Tile Transceiver PHY User Guide.

The input reference clock must be stable and free-running at FPGA power-up for proper PLL calibrations and a successful configuration.
IO_AUX_RREF[20] Input

Precision reference resistor for the AIB auxiliary channel.

 Connect to a 2-kΩ resistor (±1%) to GND.
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