Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
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1.3.2. E-Tile Transceiver Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 15.  E-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines

GXE[R9A]_RX_CH[0:23][p,n]

Input

High speed differential serial inputs to receiver circuitry. Specific to the E-tile transceiver on the right (R) side of the device.

Supports both NRZ and PAM4 modulation. For the supported data rates, refer to the Intel® Agilex™ Device Data Sheet.

No off-chip AC-coupling capacitor is required if the RX input common mode is between VCCRT_GXE and GND, and the RX input amplitude difference is less than 1200 mVp-p. The absolute maximum input to the E-Tile SerDes is VCCRT_GXE + 300 mV to prevent forward biasing of the ESD diodes.

When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. For more information about the external AC-coupling, refer to the E-Tile Transceiver PHY User Guide.

Leave unused pins floating.

GXE[R9A]_TX_CH[0:23][p,n] Output

High speed differential serial outputs from the transmitter circuitry. Specific to the E-tile transceiver on the right (R) side of the device.

Supports both NRZ and PAM4 modulation. For the supported data rates, refer to the Intel® Agilex™ Device Data Sheet.

Leave unused pins floating.
REFCLK_GXE[R9A]_CH[0:8][p,n] Input

High speed differential reference clock connects to the E-tile transceiver of the right (R) side of the device.

REFCLK_GXE is supplied to both RX and TX independently.

REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode.

Supported I/O standard:

  • LVPECL

The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination. You have to enable the internal terminations in the Intel® Quartus® Prime software.

Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to the Reference Clock Pins section of the E-Tile Transceiver PHY User Guide.

Tie each unused REFCLK pin to GND through a 1-kΩ resistor.

REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to the Dynamic Reconfiguration Flow for Special Cases section of the E-Tile Transceiver PHY User Guide.

Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to the Unused Transceiver Channels section of the E-Tile Transceiver PHY User Guide.

The input reference clock must be stable and free-running at FPGA power-up for proper PLL calibrations and a successful configuration.

IO_AUX_RREF[20] Input

Precision reference resistor for the AIB auxiliary channel.

Connect to a 2-kΩ resistor (±1%) to GND.

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