Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.2.2. Dedicated Configuration/JTAG Pins

Note: Intel® recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 3.  Dedicated Configuration/JTAG Pins
Pin Name Pin Functions Pin Description Connection Guidelines
TCK Input

Dedicated JTAG test clock input pin located in the Secure Device Manager (SDM) bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-down resistor.

JTAG clock speed is 33 MHz for JTAG split mode. In the JTAG split mode, the SDM JTAG mode is independent of the HPS JTAG.

JTAG clock speed is 22 MHz for JTAG daisy-chain mode. In the JTAG daisy-chain mode, the HPS DAP TAP is daisy chained with the SDM mTAP.

Connect this pin through a 1-kΩ pull-down resistor to GND.

If you plan to use the attestation and/or Black Key Provisioning (BKP) security features, do not connect this pin to GND. Connect this pin to the VCCIO_SDM supply using a 10-kΩ pull-up resistor.

TMS Input

Dedicated JTAG test mode select input pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor.

TDO Output

Dedicated JTAG test data output pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin supports the 1.8-V single-ended I/O standard.

 If the JTAG interface is not used, leave the TDO pin unconnected.
TDI Input

Dedicated JTAG test data input pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor.

nSTATUS Output

Configuration status pin. This pin is used for synchronization with the configuration host driving nCONFIG and to report errors.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

The drive strength is 8 mA.

Attention: Ensure that during power up, no external component drives the nSTATUS signal low.

When you are using the Avalon® streaming configuration scheme, connect this pin to the configuration host.

For other configuration schemes, you can use this pin to monitor the configuration status.

This pin must be pulled up through a 10-kΩ resistor to VCCIO_SDM for all configuration schemes.

nCONFIG Input

The nCONFIG pin is used to clear the device and prepare for reconfiguration.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

When you use the Avalon® streaming configuration scheme, connect this pin to the configuration host.

When you use other configuration schemes, pull this pin to VCCIO_SDM through an external 10-KΩ pull-up resistor. This pin can be used to restart configuration by driving it low and then high again. Ensure that you follow all the requirements for the nCONFIG operation as specified in the Agilex™ 7 Configuration User Guide and AN 886: Agilex™ 7 Device Design Guidelines .

OSC_CLK_1 Input

Reference clock source for SDM PLL.

This pin is used as the clock for device configuration and transceiver calibration.

This pin supports the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-down resistor.

You must provide an external clock source to this pin if you are using transceivers.

If you choose to use the external clock source for configuration and/or instantiate any transceivers in your design, you must provide a 25-MHz, 100-MHz, or 125-MHz free-running clock source to this pin and enable it in the Quartus® Prime software when you compile your design.

If you are using the internal oscillator for configuration and do not instantiate any transceivers in your design, leave this pin unconnected.
Note: Starting with Quartus® Prime Pro Edition software version 23.4, the software enforces a check for the appropriate QSF (.qsf) assignment required to constrain the device’s OSC_CLK_1 pin for projects that contain F-Tile transceivers in the design. Failure to provide this QSF assignment causes the compilation to fail. For more information about the OSC_CLK_1 QSF assignment requirement, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide .
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