Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Document Table of Contents

1.7.2. HPS Oscillator Clock Input Pin

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 23.  HPS Oscillator Clock Input PinYou must provide one input clock source to the HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS.

Input Select one of the 48 HPS dedicated I/O. For details of the supported frequency, refer to the Intel® Agilex™ Device Data Sheet.

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