Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.2.1. Clock and PLL Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 2.  Clock and PLL Pins
Pin Name Pin Functions Pin Description Connection Guidelines

CLK_[T,B]_2[A,B,C,D,E,F]_[0:1][p,n]

CLK_[T,B]_3[A,B,C,D,E,F]_[0:1][p,n]

I/O, Clock Input

Dual-purpose I/O pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins.

For more information about the supported pins, refer to the device pin-out file.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

Supported I/O standards:

  • 1.2 V
  • True Differential Signaling

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Tie the unused pins to GND. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,D,E,F]_[T,B]_FB[0:1]

PLL_[3][A,B,C,D,E,F]_[T,B]_FB[0:1]

I/O, Clock Input

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

  • 1.2 V
  • True Differential Signaling

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Tie the unused pins to GND. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]

PLL_[3][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]

I/O, Clock Output

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

  • 1.2 V
  • True Differential Signaling

These pins support the programmable pull-up resistor. For more information, refer to the Intel® Agilex™ Device Data Sheet.

Tie the unused pins to GND. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

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