Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.5.2. F-Tile Transceiver Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 19.  F-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
RCOMP_P_FHT_GXF Input External biasing resistor for F-tile FHT.

Connect each RCOMP_P_FHT_GXF pin with a 1.5-KΩ resistor (0.1%) to the RCOMP_N_FHT_GXF pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 1.5-KΩ resistor between the RCOMP_P_FHT_GXF and RCOMP_N_FHT_GXF pins.

RCOMP_N_FHT_GXF
RCOMP_P_Q2_CH1_FGT_GXF Input External biasing resistor for F-tile FGT.

Connect each RCOMP_P_Q2_CH1_FGT_GXF pin with a 499-Ω resistor (0.1%) to the RCOMP_N_Q2_CH1_FGT_GXF pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 499-Ω resistor between the RCOMP_P_Q2_CH1_FGT_GXF and RCOMP_N_Q2_CH1_FGT_GXF pins.

RCOMP_N_Q2_CH1_FGT_GXF
REFCLK_FHT[L,R]_CH[0,1]P Input

F-tile FHT reference clock input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_FHT[L,R]_CH[0,1]N
REFCLK_FGT[L,R]_Q[0,1,2,3]_RX_CH[0,1,2,3,4,5,6,7]P Input

F-tile FGT reference clock input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_FGT[L,R]_Q[0,1,2,3]_RX_CH[0,1,2,3,4,5,6,7]N
REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]P Input/Output

F-tile FGT reference clock input or recovery clock output pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling input case.

Tie to GND or leave floating if this tile is not used. Tie to GND if the tile is used, and the pin is not used.

REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]N
FHT[L,R]_RX_CH[0,1,2,3]P Input

F-tile FHT transceiver input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

Tie to GND if these pins are not used.

FHT[L,R]_RX_CH[0,1,2,3]N
FHT[L,R]_TX_CH[0,1,2,3]P Output

F-tile FHT transceiver output pins.

For more information about the supported pins, refer to the device pin-out file.

Leave unused pins floating.
FHT[L,R]_TX_CH[0,1,2,3]N
FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]P Input

F-tile FGT transceiver input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

Tie to GND if these pins are not used.

FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]N
FGT[L,R]_TX_Q[0,1,2,3]_CH[0,1,2,3]P Output

F-tile FGT transceiver output pins.

For more information about the supported pins, refer to the device pin-out file.

Leave unused pins floating.
FGT[L,R]_TX_Q[0,1,2,3]_CH[0,1,2,3]N
I_PIN_PERST_N_GXF Input External reset for F-tile in one PCIe case.

1.8-V LVCMOS reset input in PCIe case.

In a PCIe* adapter card implementation, connect this signal from the PCIe* edge connector to each F-tile PCIe* reset input pin. Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V input of each F-tile transceiver that is used on the board. Provide a 1.8-V pull-up resistor for this input pin as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the F-tile is unused, or the F-tile is used but PCI Express* is unused, tie to GND.

In case one reset pin controls multiple PCIe* IPs in bifurcation mode, ensure that this signal is de-asserted high after all IPs reference clocks are stable.

ENB_GXF_FHT Input Enable or disable FHT support in F-tile. Tie to VCCCLK_GXF if FHT channels are used; tie to GND if FHT channel is not used.
APROBE_GXF_FGT[12A]_Q[0,2,3]_CH3 Leave these pins floating.
APROBE2_GXF_FGT[12A]_Q3_CH3 Leave these pins floating.
APROBE1_GXF_FHT[12A] Leave these pins floating.
APROBE2_GXF_FHT[12A] Leave these pins floating.

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