Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 6/21/2022
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1.5.1. F-Tile Power Supply Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 18.  F-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCC_HSSI_GXF[L,R] Power

F-tile digital 0.8-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCC_HSSI_GXF to low noise switching regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCH_FGT_GXF[L,R] Power

F-tile general purpose transceiver (FGT) digital 1.8-V logic.

For more information about the supported pins, refer to the device pin-out file.

VCCH_FGT_GXF should share 1.8-V rail with VCCPT through ferrite bead. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCEHT_FHT_GXF[L,R] Power

F-tile high-speed transceiver (FHT) digital 1.5-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCEHT_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if there is no FHT channel used.

VCCERT_FGT_GXF[L,R] Power

F-tile FGT analog 1.0-V logic.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT_FGT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if this tile is not used.

VCCERT1_FHT_GXF[L,R] Power

F-tile FHT analog 1.0-V supply 1.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT1_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if there is no FHT channel used.

VCCERT2_FHT_GXF[L,R] Power

F-tile FHT analog 1.0-V supply 2.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT2_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if there is no FHT channel used.

VCCFUSECORE_GXF[L,R] Power

F-tile fuse sense 1.0-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCFUSECORE_GXF should share 1.0-V rail from power group 2. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCFUSEWR_GXF[L,R] Power

F-tile fuse sense 1.0-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCFUSEWR_GXF should share 1.0-V rail from power group 2. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used

VCCCLK_GXF[L,R] Power

F-tile 1.8-V supply.

For more information about the supported pins, refer to the device pin-out file.

VCCCLK_GXF should share 1.8-V rail with VCCPT through ferrite bead. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for filter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCC_SENSE_FHT_GXF Power Sense Differential sense line to external regulator.

VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF are differential remote sense pins for the VCCERT1_FHT_GXF power. Connect the differential remote sense lines of the regulator to the respective VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCERT1_FHT_GXF power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF lines to the remote sense inputs of the regulator.

Tie to GND if there is no FHT channel used.

VSS_SENSE_FHT_GXF

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