External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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4.1.5. usr_rst_n for EMIF

User clock domain reset interface

Table 28.  Interface: usr_rst_nInterface type: reset
Port Name Direction Description
usr_rst_n output User reset