Visible to Intel only — GUID: zue1682627245359
Ixiasoft
Visible to Intel only — GUID: zue1682627245359
Ixiasoft
7.2.3.7. Pin Swapping Guidelines
Byte Lane Swapping
You can swap the data lane when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM/DBI pins in the same byte lane with the other utilized byte lane.
Controller | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|
Primary | LPDDR4 x32 |
wDQ[3] | wDQ[2] | GPIO | GPIO | wAC1 | wAC0 | wDQ[1] | wDQ[0] |
Primary + Secondary | LPDDR4 x16 2ch |
sDQ[1] | sDQ[0] | sAC1 | sAC0 | wAC1 | wAC0 | wDQ[1] | wDQ[0] |
Example 1: LPDDR4 x32
BL4 and BL5 are not used by EMIF. The BL0, 1, 6 and 7 are used DQ lanes. Byte lane swapping between BL0 and BL1 is allowed; byte lane swapping between BL6 and BL7 is allowed.
Example 2: LPDDR4 x16, 2ch
Channel 0 uses BL0 and BL1 as the DQ lanes, and BL2 and BL3 as AC lanes. Byte lane swapping between BL0,1 is allowed.
Channel 1 uses BL6 and BL7 as the DQ lanes, and BL4 and BL5 as AC lanes. Byte lane swapping between BL6,7 is allowed.
Cross channel DQ lane swapping is not allowed.
Address and Command and CLK Lane
You cannot swap address and command and control signals in a bank. Pin mapping must adhere to the requirements defined in the table in the Address and Command Pin Placement for LPDDR4 topic.
You cannot swap address and command lanes. You cannot swap among AC0/AC1 lanes. The address and command lane placement must adhere to the specific placement defined in the table in the LPDDR4 Data Width Mapping topic.
The T and C pins for the CLK_T and CLK_C cannot be swapped with each other, nor can the T and C pins for the DQS_T and DQS_N be swapped with each other.