Visible to Intel only — GUID: ybt1698967440823
Ixiasoft
Visible to Intel only — GUID: ybt1698967440823
Ixiasoft
7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4
Display Name | Description |
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HDL Selection | This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL. (Identifier: EX_DESIGN_HDL_FORMAT) |
Synthesis | Generate Synthesis Example Design (Identifier: EX_DESIGN_GEN_SYNTH) |
Simulation | Generate Simulation Example Design (Identifier: EX_DESIGN_GEN_SIM) |
Core Clock Freq | Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode) Note: This parameter can be auto-computed. (Identifier: EX_DESIGN_CORE_CLK_FREQ_MHZ) |
Core Refclk Freq | PLL reference clock frequency in MHz for PLL supplying the core clock (Identifier: EX_DESIGN_CORE_REFCLK_FREQ_MHZ) |
Hydra Remote Access | Specifies whether the Hydra control and status registers are accessible via JTAG, exported to the fabric, or just disabled (Identifier: EX_DESIGN_HYDRA_REMOTE) |
Display Name | Description |
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Technology Generation | Denotes the specific memory technology generation to be used Note: This parameter can be auto-computed. (Identifier: MEM_TECHNOLOGY) |
Memory Format | Specifies the packaging format of the memory device (Identifier: MEM_FORMAT) |
Memory Device Topology | Topology used by memory device (Identifier: MEM_TOPOLOGY) |
Memory Ranks | Total number of physical ranks in the interface (Identifier: MEM_NUM_RANKS) |
Number of Channels | Number of channels (Identifier: MEM_NUM_CHANNELS) |
Device DQ Width | If the device is a DIMM: Specifies the full DQ width of the DIMM. If the interface is composed of discrete components: Specifies the DQ width of each discrete component. (Identifier: MEM_DEVICE_DQ_WIDTH) |
Number of Components Per Rank | Number of components per rank. If each component contains more than one rank, then set this parameter to 1. (Identifier: MEM_COMPS_PER_RANK) |
ECC Mode | Specifies the type of ECC (if any) and the required number of side-band bits per channel that will be used by this EMIF instance. While not all required side-band bits necessarily carry ECC bits, all need to be connected to the memory device. If enabling ECC requires more side-band bits than necessary ECC bits, then ECC bits are transmitted on the least significant side-band bits. Note: This parameter can be auto-computed. (Identifier: CTRL_ECC_MODE) |
Total DQ Width | (Derived Parameter) This will be the width (in bits) of the mem_dq port on the memory interface. For a component interface, it is calculated based on: (MEM_COMPS_PER_RANK * MEM_DEVICE_DQ_WIDTH + (8 bits if Side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode)) * MEM_NUM_CHANNELS For a DIMM-based interface, it is just MEM_DEVICE_DQ_WIDTH + (8 bits if side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode) * MEM_NUM_CHANNELS. (Identifier: MEM_TOTAL_DQ_WIDTH) |
Memory Clock Frequency | Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters. Note: This parameter can be auto-computed. (Identifier: PHY_MEMCLK_FREQ_MHZ) |
Instance ID | Instance ID of the EMIF IP. EMIF in the same bank, or connected to related user logic (e.g. to the same INIU), should have unique IDs in order to distinguish them when using the side-band interface. Valid values are 0-6. (Identifier: INSTANCE_ID) |
Display Name | Description |
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Use Memory Device Preset from file | Specifies whether MEM_PRESET_ID will be a value from Quartus (if false), or a value from a custom preset file path (if true) (Identifier: MEM_PRESET_FILE_EN) |
Memory Preset custom file path | Path to a .qprs file on the users disk (Identifier: MEM_PRESET_FILE_QPRS) |
Memory Preset | The name of a preset that the user would like to load, describing the memory device that this emif will be targeting. Note: This parameter can be auto-computed. (Identifier: MEM_PRESET_ID) |
Display Name | Description |
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Asynchronous Enable | Specifies whether the user logic is clocked based on the clock provided by the IP (Sync), or by a separate user clock (Async). If true - async mode is used, if false - sync mode is used. (Identifier: PHY_ASYNC_EN) |
AC Placement | Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms IO BANK and TOP vs BOT part of the IO BANK). Legal ranges are derived from device floorplan. By default (value=AUTO), the most optimal location is selected (to maximize available frequency and data width). Note: This parameter can be auto-computed. (Identifier: PHY_AC_PLACEMENT) |
PLL Reference Clock Frequency | Specifies what PLL reference clock frequency the user will supply. It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance. Note: This parameter can be auto-computed. (Identifier: PHY_REFCLK_FREQ_MHZ) |
Display Name | Description |
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Voltage | The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface. (Identifier: PHY_IO_VOLTAGE) |
Display Name | Description |
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Drive Strength | This parameter allows you to change the output on chip termination settings for the selected I/O standard on the Address/Command Pins. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM) |
Display Name | Description |
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Drive Strength | This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM) |
Display Name | Description |
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I/O Standard | Specifies the I/O electrical standard for the data bus pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard. (Identifier: GRP_PHY_DATA_X_DQ_IO_STD_TYPE) |
Drive Strength | This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM) |
Slew Rate | Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals. (Identifier: GRP_PHY_DATA_X_DQ_SLEW_RATE) |
Input Termination | This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM) |
Initial Vrefin | Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins. (Identifier: GRP_PHY_DATA_X_DQ_VREF) |
Display Name | Description |
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PLL Reference Clock Input Termination | This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM) |
Display Name | Description |
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Target Write Termination | Specifies the target termination to be used during a write (Identifier: GRP_MEM_ODT_DQ_X_TGT_WR) |
Drive Strength | Specifies the termination to be used when driving read data from memory (Identifier: GRP_MEM_ODT_DQ_X_RON) |
Display Name | Description |
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VrefDQ Range | Specifies which of the memory protocol defined ranges will be used (Identifier: GRP_MEM_DQ_VREF_X_RANGE) |
VrefDQ Value | Specifies the initial VrefDQ value to be used (Identifier: GRP_MEM_DQ_VREF_X_VALUE) |
Display Name | Description |
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Common Termination | Common termination value that can be applied to CA/CK/CS for LPDDR4 and can be applied to CA/CK for LPDDR5 (Identifier: GRP_MEM_ODT_CA_X_CA_COMM) |
CA Termination Enable | Enable the common termination value on the CA bus. For LPDDR4, enabling CA termination will have no effect unless the ODT_CA bond pad is HIGH. (Identifier: GRP_MEM_ODT_CA_X_CA_ENABLE) |
CS Termination Enable | Enable the common termination value on the CS bus for LPDDR4. For LPDDR5, this enables the fixed-value 80 Ohm (RZQ/3) CS termination if it is supported by the memory. (Identifier: GRP_MEM_ODT_CA_X_CS_ENABLE) |
CK Termination Enable | Enable the common termination value on the CK bus (Identifier: GRP_MEM_ODT_CA_X_CK_ENABLE) |
Display Name | Description |
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VrefCA Range | Specifies which of the memory protocol defined ranges will be used (Identifier: GRP_MEM_VREF_CA_X_CA_RANGE) |
VrefCA Value | Specifies the initial VrefCA value to be used (Identifier: GRP_MEM_VREF_CA_X_CA_VALUE) |
Display Name | Description |
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Enable Debug Tools | If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface. (Identifier: DEBUG_TOOLS_EN) |
AXI-Lite Port Access Mode | Specifies whether the AXI-Lite port is connected to the fabric, the NOC, or disabled Note: This parameter can be auto-computed. (Identifier: AXI_SIDEBAND_ACCESS_MODE) |
Display Name | Description |
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User Extra Parameters | Semi-colon separated list of key/value pairs of extra parameters (Identifier: USER_EXTRA_PARAMETERS) |
Display Name | Description |
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Enable performance monitoring | Enable performance monitor on all channels for measuring read/write transaction metrics (Identifier: EX_DESIGN_PMON_ENABLED) |