Visible to Intel only — GUID: pxd1680408903043
Ixiasoft
Visible to Intel only — GUID: pxd1680408903043
Ixiasoft
7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP
Intel® Agilex™ 5 FPGA I/O banks contain 96 I/O pins. Each bank is divided into two sub-banks with 48 I/O pins in each. Sub-banks are further divided into four I/O lanes, where each I/O lane is a group of twelve I/O ports.
Intel® Agilex™ 5 FPGAs do not support flexible DQ group assignments. Only specific byte-lanes can be used as Address/Command lanes or data lanes. As you increase the interface width, only specific byte-lanes can be used.
The I/O bank, I/O lane, and pairing pin for every physical I/O pin can be uniquely identified by the following naming convention in the device pin table:
- The I/O pins in a bank are represented as P#, where P# represents the pin number in a bank. It ranges from P0 to P95, for 96 pins in a bank. Because an IO96 bank comprises two IO48 sub-banks, all pins with P# value less than 48 (P# <48) belong to the same I/O sub-bank. All other pins belong to the second IO48 sub-bank.
- The Index Within I/O Bank value falls within one of the following ranges: 0 to 11,12 to 23, 24 to 35, or 36 to 47, and represents one of I/O lanes 0, 1, 2, or 3, respectively.
- To determine whether I/O banks are adjacent, you can refer to Architecture: I/O Bank in the Product Architecture chapter. In general, the two sub-banks within an I/O bank are adjacent to each other when there is at least one byte-lane in each sub-bank that is bonded out and available for EMIF use.
- The pairing pin for an I/O pin is in the same I/O bank. You can identify the pairing pin by adding 1 to its Index Within I/O Bank number (if it is an even number), or by subtracting 1 from its Index Within I/O Bank number (if it is an odd number).