External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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3.3. Agilex™ 5 EMIF Sequencer

The Agilex™ 5 EMIF sequencer is fully hardened in silicon, with executable code to handle protocols and topologies. Hardened RAM contains the calibration algorithm.

The Agilex™ 5 EMIF sequencer is responsible for the following operations:

  • Initializes memory devices.
  • Calibrates the external memory interface.
  • Governs the hand-off of control to the memory controller.
  • Handles recalibration requests and debug requests.
  • Handles all supported protocols and configurations.
Figure 11.  Agilex™ 5 EMIF Sequencer Operation