External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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Document Table of Contents

3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem

In Agilex™ 5 devices, four types of I/O banks are available:
  • High Speed I/O (HSIO)
  • High Voltage I/O (HVIO)
  • Hard Processor System I/O (HPS I/O)
  • Secure Device Manager I/O (SDM I/O)

Only HSIO banks can support EMIF interfaces.

Figure 2. Example of Device Layout for Agilex™ 5 FPGAs
Note:
  • The above figure does not show transceiver banks.
  • HSIO and HVIO bank availability varies across device packages.
The HSIO subsystem provides the following features:
  • General-purpose I/O registers and I/O buffers.
  • Compensation block (comp block)
    • On-chip termination (OCT)
  • I/O PLLs
    • I/O bank I/O PLL for external memory interfaces and user logic
    • Fabric feeding for non-EMIF/non-LVDS SERDES IP applications
  • True differential signaling
  • External memory interface components, as follows:
    • A primary hard memory controller, which has connectivity to 8 lanes (up to 4 byte lanes for data, and optionally one additional lane for out-of-band ECC data.)
    • A secondary hard memory controller, which has connectivity to 4 lanes (up to 2 byte lanes for data.
    • Hard PHY.
    • Hardened processor and calibration logic.
    • DLL.