External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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6.2.2.1.2. Estimating Pin Requirements

You should use the Quartus® Prime software for final pin fitting. However, you can estimate whether you have enough pins for your memory interface by performing the following steps:

  1. Determine how many read/write data pins are associated per data strobe or clock pair.
  2. Calculate the number of other memory interface pins needed, including any other clocks (write clock or memory system clock), address, command, and RZQ. Refer to the External Memory Interface Pin Table to determine necessary address/command/clock pins based on your desired configuration.
  3. Calculate the total number of HSIO banks required to implement the memory interface, given that an HSIO bank supports up to 96 pins.

Test the proposed pin-outs with the rest of your design in the Quartus® Prime software (with the correct I/O standard and OCT connections) before finalizing the pin-outs. There can be interactions between modules that are illegal in the Quartus® Prime software that you might not know about unless you compile the design and use the Quartus® Prime Pin Planner.