External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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7.2.3.6. Pin Placements for Agilex™ 5 FPGA EMIF IP for LPDDR4

Intel® Agilex™ 5 FPGA LPDDR4 IP supports fixed address and command pin placement, and fixed data lanes placement.

You can only use fixed byte lanes within the I/O Bank as data lanes. Below is the summary of the location for address and command, and data lanes.

For two-channel x16 LPDDR4, the DQ group placement must follow the controller I/O sub-bank:

Controller Data Width BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]   BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Primary LPDDR4 x32 DQ[3] P DQ[2] P GPIO GPIO AC1 P AC0 P DQ[1] P DQ[0] P                  
Primary LPDDR4 1ch x16 GPIO GPIO GPIO GPIO AC1 P AC0 P wDQ[1] wDQ[0]                  
Secondary * LPDDR4 1ch x16 DQ[1] S DQ[0] S AC1 S AC0 S GPIO GPIO GPIO GPIO                  
Primary + Secondary LPDDR4 2ch x16 DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0- P DQ[1] P DQ[0] P                  
Primary + Secondary LPDDR4 4ch x16 DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0- P DQ[1] P DQ[0] P   DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0 P DQ[1] P DQ[0] P
Note:
  • P Primary controller
  • S Secondary controller
  • * Not supported on ES0 silicon. ES0 silicon supports LPDDR4x16 only on bottom sub-bank (BL0-BL3).

The diagrams below illustrates the pin connections for address and command and the data group.

Note: Refer to the LPDDR4 pin table in the Product Architecture chapter for detailed pin placement for both address and command and DQ pins.
Figure 31. Dual-Channel x16 LPDDR4, Single Rank
Figure 32. Single-Channel x32 LPDDR4, Single Rank