Visible to Intel only — GUID: pxg1698967444970
Ixiasoft
Visible to Intel only — GUID: pxg1698967444970
Ixiasoft
7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions
Display Name | Description |
---|---|
Configuration Filepath | Filepath to Save to (.qprs extension) (Identifier: MEM_CONFIG_FILE_QPRS) |
Display Name | Description |
---|---|
Memory Format | Specifies the packaging format of the memory device (Identifier: MEM_FORMAT) |
Number of Channels in Memory Package | Number of Channels in Memory Package. This value must be consistent with the same MEM_NUM_CHANNELS parameter in the top-level EMIF IP GUI. (Identifier: LPDDR4_MEM_DEVICE_NUM_CHANNELS) |
Number of Ranks Per Channel | Number of Ranks Per Channel in Memory Package. This value must be consistent with the same MEM_NUM_RANKS parameter in the top-level EMIF IP GUI. (Identifier: LPDDR4_MEM_DEVICE_NUM_RANKS_PER_CHANNEL) |
Number of Individual DRAM Components Per Rank | Number of Individual DRAM Components Per Rank in Memory Package. This value must be consistent with the same MEM_COMPS_PER_RANK parameter in the top-level EMIF IP GUI. (Identifier: LPDDR4_MEM_DEVICE_NUM_COMPS_PER_RANK) |
Density of Each Memory Die per Channel | Specifies the density of each channel in the memory die in Gb (Identifier: LPDDR4_MEM_DEVICE_DENSITY_GBITS) |
Enable Write Data Bus Inversion | Enables Write Data Bus Inversion (Identifier: LPDDR4_MEM_DEVICE_WR_DBI_EN) |
Enable Data Mask | Enables Data Masking for write operations (Identifier: LPDDR4_MEM_DEVICE_DM_EN) |
Display Name | Description |
---|---|
DQ Width per DRAM Component | Specifies the DQ width of each LPDDR4 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP4 interfaces, select 2 components per rank at the EMIF IP level. (Identifier: LPDDR4_MEM_DEVICE_DQ_WIDTH) |
Total DQ Width Per Channel | Total DQ Width Per Channel. For LPDDR4 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank. (Identifier: LPDDR4_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL) |
Burst Length | Burst Length (Identifier: LPDDR4_MEM_DEVICE_BURST_LENGTH) |
Display Name | Description |
---|---|
Device Row Address Width | Specifies the row address width of this LPDDR4 DRAM component. This value is auto-derived from the specified component density. (Identifier: LPDDR4_MEM_DEVICE_ROW_ADDR_WIDTH) |
Device Bank Address Width | Specifies the bank address width. This value is fixed as per the JEDEC standard and cannot be changed. (Identifier: LPDDR4_MEM_DEVICE_BANK_ADDR_WIDTH) |
Device Column Address Width | Specifies the column address width of this LPDDR4 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed. (Identifier: LPDDR4_MEM_DEVICE_COL_ADDR_WIDTH) |
Display Name | Description |
---|---|
Memory Clock Frequency | Specifies the Write Clock Frequency Note: This parameter can be auto-computed. (Identifier: PHY_MEMCLK_FREQ_MHZ) |
Memory Speedbin | Maximum Data Rate for which this memory device is rated for (Identifier: LPDDR4_MEM_DEVICE_SPEEDBIN) |
Memory Write Latency Set | Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency. (Identifier: LPDDR4_MEM_DEVICE_WLS) |
Memory Read Latency | Read Latency of the memory device in clock cycles Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_CL_CYC) |
Memory Write Latency | Write Latency in clock cycles Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_CWL_CYC) |
Display Name | Description |
---|---|
Read Preamble Cycles | Duration of read preamble in cycles (Identifier: LPDDR4_MEM_DEVICE_RD_PREAMBLE_CYC) |
Read Postamble Cycles | Duration of read postamble in cycles (Identifier: LPDDR4_MEM_DEVICE_RD_POSTAMBLE_CYC) |
Write Postamble Cycles | Duration of write postamble in cycles (Identifier: LPDDR4_MEM_DEVICE_WR_POSTAMBLE_CYC) |
Display Name | Description |
---|---|
tSR | Minimum duration (Entry to Exit) of Self Refresh in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TSR_NS) |
tXSR | Self-Refresh Exit to Next Valid Command Delay Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TXSR_NS) |
tXP | Exit Power-Down to Next Valid Command Delay Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TXP_NS) |
tCCD | CAS-to-CAS Delay in memory clock cycles Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCCD_CYC) |
tRTP | Internal READ to PRECHARGE Command Delay Time in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRTP_NS) |
tRCD | RAS-to-CAS Delay in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRCD_NS) |
tRPpb | Per-Bank Precharge Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRPPB_NS) |
tRPab | All-Bank Precharge Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRPAB_NS) |
tRAS | Row Active Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRAS_NS) |
tWR | Write Recovery Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TWR_NS) |
tWTR | Write-to-Read Delay in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TWTR_NS) |
tRRD | RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRRD_NS) |
tPPD | Precharge-to-precharge delay in memory clock cycles Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TPPD_CYC) |
tFAW | Four-bank ACTIVE window time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TFAW_NS) |
tRC | Activate-to-Activate command period (same bank) in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRC_NS) |
tREFW | Refresh window time in milliseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TREFW_MS) |
Min Number of Refs Reqd | Minimum Number of Refreshes Required Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_MINNUMREFSREQ) |
tREFI | Refresh Interval Time in us Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TREFI_NS) |
tRFCab | All-Bank Refresh Cycle Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRFCAB_NS) |
tRFCpb | Per-Bank Refresh Cycle Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TRFCPB_NS) |
tCKE | CKE Minimum Pulse Width time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKE_NS) |
tCMDCKE | Delay from valid command to power-down-entry (CKE low) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCMDCKE_NS) |
tCKELCK | Valid clock requirement after power-down-entry in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKELCK_NS) |
tCSCKE | Valid CS requirement before power-down-entry (CKE low) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCSCKE_NS) |
tCKCKEH | Valid clock requirement before power-down-exit in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKCKEH_NS) |
tCSCKEH | Valid CS requirement before power-down-exit (CKE high) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCSCKEH_NS) |
tMRWCKEL | Delay from MRW command to power-down-entry (CKE low) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TMRWCKEL_NS) |
tZQCKE | Delay from ZQCal Start command to power-down-entry (CKE low) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TZQCKE_NS) |
tMRR | Mode Register Read Command Period Time in memory clock cycles Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TMRR_CYC) |
tMRW | Mode Register Write Command Period Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TMRW_NS) |
tMRD | Mode Register Set Command Period Time in ns Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TMRD_NS) |
tESCKE | Delay from SRE command to CKE Input low Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TESCKE_NS) |
tZQCAL | ZQ calibration time in microseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TZQCAL_US) |
tZQLAT | ZQcal Latch time in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TZQLAT_NS) |
tDQSCK_MAX | Maximum DQS output access time from CK in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TDQSCK_MAX_PS) |
tDQSCK_MIN | Minimum DQS output access time from CK in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TDQSCK_MIN_PS) |
tCKCKEL | Clock valid requirements after power-down-entry (CKE low) in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKCKEL_NS) |
tCKELCMD | Valid command requirement after CKE input low in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKELCMD_NS) |
tCKEHCMD | Valid command requirement after CKE input high in nanoseconds Note: This parameter can be auto-computed. (Identifier: LPDDR4_MEM_DEVICE_TCKEHCMD_NS) |