External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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Document Table of Contents

8.2.1.2. LPDDR5 Component Options

The table and figures below illustrate pin placement and routing recommendation for a single 32-bit channel, and two 16-bit channels, respectively.
Note: You should always consult your memory vendor’s data sheet to verify pin placement and routing plans.
Table 137.  Pin Options for LPDDR5 x32 and x16
Pins 1CH x32 2CH x16
Data

32-bit

DQ[15:0]_A

DQ[15:0]_B

DQ[15:0]_A

DQ[15:0]_B

Data mask

DM[1:0]_A

DM[1:0]_B

DM[1:0]_A

DM[1:0]_B

Read data strobe

RDQS[1:0]_t_A

RDQS[1:0]_c_A

RDQS[1:0]_t_B

RDQS[1:0]_t_B

RDQS[1:0]_t_A

RDQS[1:0]_c_A

RDQS[1:0]_t_B

RDQS[1:0]_c_B

Write clock

WCK[1:0]_t_A

WCK[1:0]_c_A

WCK[1:0]_t_B

WCK[1:0]_c_B

Command/address

CA[6:0]_A

CS0_A

CA[6:0]_B

CS0_B

CA[6:0]_A

CS0_A

CA[6:0]_B

CS0_B

Clock

CK_t_A

CK_c_A

CK_t_B

CK_c_B

CK_t_A

CK_c_A

CK_t_B

CK_c_B

Reset

RESET_n

RESET_n (Resistor jumper to select from mem_0 or mem_1.)

Figure 44. Pin Options for LPDDR5 2ch x16
Figure 45. Pin Options for LPDDR5 1ch x32