External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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8.2.3.4. Clock Signals

LPDDR5 SDRAM devices use CK_t and CK_c signals to clock the address and command signals into the memory.
The memory uses these clock signals to generate the DQS signal during a read through the DLL inside the memory.