Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

12.2. PCS Features in Intel® Agilex™ 5 FPGA Transceivers

The PMA channels in the Intel® Agilex™ 5 FPGAs and SoCs interface with the core logic through the configurable and bypassable PCS interface layers.

The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. The transceiver (PMA with optional FEC or PCS) to FPGA fabric interface support from 8 bits up to 66 bits options. This feature allows you to implement a wide range of applications.

The PCS hard IP supports various standard and proprietary protocols across a wide range of data rates and encoding schemes.