F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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Document Table of Contents

4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles

You configure the Dynamic Reconfiguration IP along with a respective protocol IP through the appropriate IP graphical user interface (GUI) settings. Based on the IP settings, RTL connections in the design, and the required QSF settings, the Intel® Quartus® Prime software generates the required programming file sets. The generated programming file sets include the connection information and the MIF file.
To generate a dynamic reconfiguration design, follow these steps:
  1. Create an Intel® Quartus® Prime project.
  2. In the Intel® Quartus® Prime IP Catalog, locate the respective required protocol IP.
  3. Configure the protocol IP instance with the targeted settings.
  4. Generate the protocol IP.
  5. If your design requires multiple protocol IPs, repeat steps 2 through 4 for each protocol IP.
  6. In the IP Catalog, locate the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP (Dynamic Reconfiguration IP).
  7. Configure the Dynamic Reconfiguration IP instance with the targeted settings.
  8. Generate the Dynamic Reconfiguration IP.
  9. Instantiate the protocol IP(s) and a Dynamic Reconfiguration IP in your RTL. For RTL connections examples, refer to the design examples generated per the F-Tile Dynamic Reconfiguration Design Example User Guide
    Note: Each F-tile only supports a single Dynamic Reconfiguration IP instance.
  10. Enter the dynamic reconfiguration IP-specific .qsf settings such as the reconfiguration groups and others. For more information, refer to Dynamic Reconfiguration QSF Settings. You can use the Tile Assignment Editor to generate the appropriate .qsf settings. For more information, refer to Using the Tile Assignment Editor.
  11. Once your project compiles, the Intel® Quartus® Prime software generates a new top project file and other collaterals required by your design, including a MIF file containing the delta programming sequences.
Figure 2. Dynamic Reconfiguration Design Generation Flow
The diagram below illustrates the RTL connections for a dynamic reconfiguration design:
Figure 3. RTL Connections in Dynamically Reconfigured Design