F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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6.23. Dynamic Reconfiguration TX Channel Reconfiguration

Table 39.   dyn_rcfg_dr_txch2reconfig_busy_reg
Offset 0x58
Addressing Mode 32-bits
Description Dynamic reconfiguration control and status register.
Table 40.   dyn_rcfg_dr_txch2reconfig_busy_reg Field Description
Bit Type Reset Description
31:20 RO 0 Reserved
19:0 RWC 0 TX Channel is Busy with Reconfiguration

When set to 1, indicates a given TX channel is currently busy and must not be set up for another reconfiguration.

Software polls the associated bit(s) for value 0 prior to setting the Trigger Reconfig bit to value 1 for the given TX channel(s). Software must not attempt to set up another reconfiguration for the given TX channel(s) when the associated bit(s) is still value of 1, indicating the busy status.

Each bit maps to a specific TX channel:
  • [0]: TX channel 0
  • [1]: TX channel 1
  • ...
  • [19]: TX channel 19

TX Channels 0-3: FHT Channels 0-3

TX Channels 4-19: FGT Channels 0-15

Writing to this register clears all busy bits.

Do not program this field when Ready For Next Trigger is set to 0.

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