F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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2.4. Control and Status Interface

Table 9.  Control and Status SignalsAll interface signals are clocked by the i_csr_clk clock.
Port Name Width (in bits) I/O Direction Description
o_dr_curr_profile_id 15 Output Specifies the selected profile.

The signal is only valid when o_dr_new_cfg_applied is 1.

You must decode the values to decide if the design is dynamically reconfigured.

o_dr_new_cfg_applied 1 Output Specifies the new configuration settings to the external logic, including tile CSRs, mux selection, etc.

Once the signal is sampled active, the external logic returns an acknowledgment to complete a full handshake signaling. Since this is a hardware action, the signal must complete within nanosecond ranges.

Once this signal is active, the Nios® continues to monitor the acknowledgment before proceeding to the next process in the dynamic reconfiguration flow. After an acknowledgment is sampled, this signal becomes inactive and the Nios® proceeds to the next step. If an acknowledgment is not sampled at a prolong period of time and time-out is enabled, this signal also becomes inactive and the Nios® proceeds to the next step at time-out. A time-out error also is signaled in this case.

i_dr_new_cfg_applied_ack 1 Input Specifies the full handshake acknowledgment in response to o_dr_new_cfg_applied signal.

The signal is active when set to 1.

o_dr_in_progress 1 Output Specifies that the dynamic reconfiguration is in progress.

This signal is active when set to 1.

o_dr_error_status 1 Output Specifies the overall dynamic reconfiguration SIP error status, including dynamically reconfigured Nios® firmware errors.

This signal is active when set to 1.

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