F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status

Table 47.   dyn_rcfg_dr_tx_reset_initial_reg
Offset 0x68
Addressing Mode 32-bits
Description Dynamic reconfiguration status register.
Table 48.   dyn_rcfg_dr_tx_reset_initial_reg Field Description
Bit Type Reset Description
31:20 RO 0 Reserved
19:0 RO 0 TX Channel Reset Control Initialized Status

TX reset control initialized status[N] = i_tx_lane_current_state[(19-N)*3+2] , where N is the number of channels from 0 to 19.

  • N = 0-3: FHT channels 0-3
  • N = 4-19: FGT channels 0-15

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