F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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4.14.1. Selecting the Master Clock Channel

This section describes how to select your own master clock channel from the dynamic reconfiguration group.

Each Multirate IP (CPRI, Ethernet, PMA, and FEC Direct PHY) that contains the .qsf assignments required to select the correct master clock channel. Therefore, when using the Multirate IP, no qsf assignments are required for selecting the master clock channel. However, in certain use cases, you may want to select your own master clock channel.

Selecting your own master clock channel could be useful if you are using a non-Multirate IP instance or if you want to select a master clock channel from another IP. In such cases, be aware of the following points when you select and assign the master clock channel for your design:

  • The master clock channel of your dynamic reconfiguration group must be up and stable at all the times for the dynamically reconfigurable streams in your design that use that master clock channel.
  • When you dynamically reconfigure the stream that provides the master clock channel, the clock becomes temporarily unavailable. This causes all other streams that use this master clock channel to fail.

Select the master clock channel for your dynamic reconfiguration design using a stream that is not dynamically reconfigured independently from other streams in your design to provide a stable master clock channel.

For example, in a four stream design, if you select "Stream 0" as the master clock channel, then either this stream:
  • Cannot be reconfigured
  • Cannot be reconfigured independently from the other three streams in your design. This requires the reconfiguration of all four streams together.

If neither of these conditions can be met, you must instantiate another PHY in your design and use it to provide the master clock channel by using the IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL.qsf assignment.

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