F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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4.3. Dynamic Reconfiguration Using QSF-driven Flow

This design example describes a reconfiguration group consisting for the 50G Ethernet Multirate IP core, 25G CPRI Multirate IP core, and the 100G Direct PHY IP. This design example specifies the Directly PHY IP as the startup instance that provides the master clock channel.

In addition to the proper RTL connections for this design consisting of an instance of the Reconfiguration Controller Suite IP, the System Clock IP, and the three protocol IPs, the design requires the .qsf assignments shown below:
  • Create a dynamic reconfiguration group for all IPs, including the Multirate IPs:
    set_instance_assignment -name IP_RECONFIG_GROUP RG_TEST_GP -to my_dphy_inst_1|dphy_f_dr_0  
    # Derive MR IP group name from QIP file and hpath of every instance to construct child DR group name
    set_instance_assignment -name IP_RECONFIG_GROUP_PARENT RG_TEST_GP:my_mr_eth_inst_2|eth_f_dr_0/RG_A  
    set_instance_assignment -name IP_RECONFIG_GROUP_PARENT RG_TEST_GP:my_mr_cpri_inst_3|cpriphy_mr_f_0/RG_A
  • Disable master clock channel and startup instance of multirate IP:
    # Discover master clock channel and starup profile inst names buried in MRIP
    #  and build full path for each inst of IP
    set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF \
    –to my_mr_eth_inst_2|eth_f_dr_0|U_base_profile|eth_f_0|hip_inst|per_aib[0].x_bb_m_hdpldadapt_tx
    set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL OFF \
    –to my_mr_cpri_inst_3|cpriphy_mr_f_0|profile_0|cpriphy_ftile_0|cpriphy_f_bb_inst|hip_bb|bb_m_hdpldadapt_tx_inst0
  • Specify master clock channel and startup instance for the dynamic reconfiguration group:
    set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF \
    –to my_mr_eth_inst_2|eth_f_dr_0|U_base_profile|eth_f_0
    set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF \
    –to my_mr_cpri_inst_3|cpriphy_mr_f_0|profile_0|cpriphy_ftile_0
    set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL ON \
    –to my_dphy_inst_1|dphy_f_dr_0 |profile_0|dphy_ftile_0|dphy_f_bb_inst|hip_bb|bb_m_hdpldadapt_tx_inst0
    set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON \
    –to my_dphy_inst_1|dphy_f_dr_0 |profile_0|dphy_ftile_0
  • Bind each member IP of the dynamic reconfiguration group to a reconfiguration controller:
    set_instance_assignment -name IP_COLOCATE F_TILE \
    -from dr_ctrl_inst_1|dr_f_0 -to my_dphy_inst_1|dphy_f_dr_0
    set_instance_assignment -name IP_COLOCATE F_TILE \
    -from dr_ctrl_inst_1|dr_f_0 -to my_mr_eth_inst_2|eth_f_dr_0 
    set_instance_assignment -name IP_COLOCATE F_TILE \
    -from dr_ctrl_inst_1|dr_f_0 -to my_mr_cpri_inst_3|cpriphy_mr_f_0