F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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6.28. Dynamic Reconfiguration TX Channel Source Alarm

Table 49.   dyn_rcfg_dr_tx_src_alarm_reg
Offset 0x6C
Addressing Mode 32-bits
Description Dynamic reconfiguration status register.
Table 50.   dyn_rcfg_dr_tx_src_alarm_reg Field Description
Bit Type Reset Description
31:20 RO 0 Reserved
19:0 RO 0 TX Channel Source Alarm

Indicates a non-requested change in TX lane state such as PLL lock lost, or other error condition. Sticky until dr_tx_clear_alarm is asserted.

  • N = 0-3: FHT channels 0-3
  • N = 4-19: FGT channels 0-15
where N is the number of channels from 0 to 19.