F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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Document Table of Contents

3. Parameters

You customize the IP core by specifying parameters in the IP parameter editor.
Figure 1.  F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
Table 10.   F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Parameters: Dynamic Reconfiguration Controller IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.



Default Setting

Parameter Description

General Options
Recovery enabled
  • Yes
  • No
  • When set to Yes, the Dynamic Reconfiguration controller can restore a region of a tile to the startup state. The supreme parent group determines the exact region that is being restored.
  • Set to No, if you do not want to recover a profile and instead want to reduce the memory initialization file (.mif) size.
  • If an error occurs while using this feature, you must set the dyn rcfg dr next profile 0 reg, bit[17] to 1, provide the appropriate profile ID, and re-trigger dynamic reconfiguration.

    The DR controller will then restore the profile to the startup profile of the supreme parent group. The supreme parent group is the root of the tree of reconfiguration groups.

    You can find the supreme parent group IDs and the startup profile IDs in the design's combined memory initialization file (.mif).

Include NIOS
  • Yes
Yes Dynamic reconfiguration facilitated by NIOS inside the DR controller soft IP.
NIOS data memory size
  • 16
  • 32
  • 64
  • 128
  • 256
  • 512
  • 1024
128 NIOS on-chip data memory used to store memory initialization file (.mif) for dynamic reconfiguration.
Enable ECC protection
  • On
  • Off
Off Enable ECC protection