F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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4.5. Hardware States and Configuration Profiles

To program the relevant dynamic reconfiguration CSR registers, you must know the profiles, reconfiguration groups, EMIB and transceiver numbering associations. The IP and the Intel® Quartus® Prime software collaterals provide the appropriate associations. To ensure the hardware configures into a correct state, all relevant CSR fields must be programmed correctly.

Intel® Quartus® Prime software generates the .mif file containing multiple profiles. Each profile contains the delta programming sequences, in a linked-list format, used by the Nios® core to retrieve necessary information.

The Intel® Quartus® Prime software-generated programming sequences for each profile uses the global Avalon® memory-mapped interface address space. The programming sequences contain all the necessary CSR writes for all EMIB to transceiver paths, including both 1:1 and N:1 EMIB to transceiver cases. For instance, a single-lane 50G Ethernet requires 2 EMIBs and 1 transceiver, and the programming sequences have catered for CSRs to be programmed for paths from the 2 EMIBs to the transceiver.

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