F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1. Dynamic Reconfiguration New Trigger

Table 12.   dyn_rcfg_dr_trigger_reg
Offset 0x00
Addressing Mode 32-bits
Description Dynamic reconfiguration control and status register.
Table 13.   dyn_rcfg_dr_trigger_reg Field Description
Bit Type Reset Description
31:2 RO 0 Reserved
1 RO   Ready for New Trigger
Indicates whether the DR IP is ready to take in a new Trigger Reconfiguration request. Host software must poll for the readiness status before triggering a new request through Trigger Reconfiguration.
  • 0: Not ready
  • 1: Ready
0 RWC 0 Trigger Reconfiguration

When set to value 1 by host software, Nios® core starts executing the dynamic reconfiguration flow in which the relevant DR CSR fields are read to check for user DR intention, followed by various other steps.

Hardware clears this bit to value 0’ after the triggering event has been captured successfully by Nios® core.

When read by software, the value is always 0. Writing a value of 0 to this register has no effect.

Do not program this field to value of 1 when Ready For Next Trigger is set to 0.

Note: An invalid programming sequence is if the corresponding channel dyn_rcfg_dr_txch2reconfig_busy_reg/dyn_rcfg_dr_rxch2reconfig_busy_reg bits are programmed to value of 1 and their associated BUSY bits are value of 1 when this field is programmed. In the case, the results are indeterminate.

Did you find the information on this page useful?

Characters remaining:

Feedback Message