F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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4.7. Using the Tile Assignment Editor

To create qsf assignments consisting of discreet IPs, you can use the Tile Assignment Editor. To open the Tile Assignment Editor: click on Intel® Quartus® Prime Menu > Assignments > Tile Assignment Editor.

Figure 5. Tile Assignment Editor
The Tile Assignment Editor consists of the following three sections:
  • New DR Group
    To create new Dynamic Reconfiguration group and it’s associated attributes. The associated attributes are:
    • Group Name: Each reconfiguration group must have a unique, user-selected name.
    • Group Type: Exclusive means that the group can only be active by itself. Inclusive means that the group can be active with other Dynamic Reconfiguration groups.
    • Reconfiguration Controller: Provides the hierarchical path to the Reconfiguration Controller IP.
    • Has Master Clock Channel: Select if you want to specify the Master Clock Channel for the Dynamic Reconfiguration group. If you do not specify the Master Clock Channel, the Quartus Support Logic Generation makes a default selection.
    • Building block instance name: Provides the name of the building block associated with the master clock channel.
    • Clock port: Provides the name of the clock port on the BB instance which is the master clock channel.
  • Grouped IP Instances
    Shows current list of IPs which have been assigned to Dynamic Reconfiguration groups and their associated attributes. The IPs are listed in hierarchical order. You can select the following associated attribute for each IP:
    • Is startup instance: Allows you to determine which IP within the Dynamic Reconfiguration group is active at startup for either hardware or simulation.
  • Ungrouped IP Instances

    Shows current list of IPs for which you can define a Dynamic Reconfiguration group. When these IPs are added to a Dynamic Reconfiguration group, they disappear from this list.