The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP allows you to dynamically reconfigure a subset of the transceiver channels to operate in different modes, for example data rates, without impacting the adjacent active channels.
Depending on the protocol and hardware implementation, dynamic reconfiguration (DR) may reconfigure media access control (MAC), forward error correction (FEC), and physical coding sublayer (PCS) blocks, and the embedded multi-die interconnect bridges (EMIB). Additional dynamic reconfiguration features include:
- Setting up the required reference clocks. The system clock must be constant across all profiles in a selected dynamic reconfiguration group.
- Selecting the appropriate clocks input for each of the MAC, FEC, PCS, and transceiver blocks
- Setting the multiplexers to select the appropriate control and data path for MAC/PCS/PMA/FEC-direct modes
The FPGA IP products support the following dynamic reconfiguration flow:
- Nios® -based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, and intra protocol link characteristic changes, such as CPRI data rate changes. A client application or an Intel® Quartus® Prime Nios® utility triggers the dynamic reconfiguration. When triggered, the Nios® performs the low level configuration register programming for various functional blocks.
This document describes the NIOS-based dynamic reconfiguration through the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP.
To perform dynamic reconfiguration (DR), you must first configure the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and then the associated protocol IP. You can use the F-Tile CPRI PHY Multirate Intel FPGA IP Core, F-Tile Ethernet Multirate Intel FPGA IP core, and F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core. You can also use the standard, single-rate IPs as well.