F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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5.3. Stack Clocking for Fracturability

The dynamic reconfiguration (DR) suite can switch between different protocols with different data rates on the serial link. To simplify dynamic reconfiguration switching, the MAC, PCS, and FEC run at a fixed system PLL clock frequency.

You choose the highest frequency system clock to receive the highest bandwidth across all possible DR protocols. Any protocols requiring smaller bandwidth rely on the data valid throttling to achieve the effective link bandwidth. The same selected frequency applies regardless of the FEC type.

The dynamic reconfiguration suite doesn't support explicit crediting mechanism between the different MAC, PCS, and FEC blocks. To prevent overrun in the protocol IPs FIFOs, the protocol bandwidth and the link bandwidth must match.

The figure below depicts stack clocking across 16 channels:
  • The system PLL and reference clock to the system PLL are fixed.
  • The protocol with the highest bandwidth determines the system clock frequency. The maximum supported system clock frequency is 1 GHz.
  • The transceiver interface FIFOs are in an elastic mode and the EMIB FIFOs are in phase compensation mode.
Figure 27. Stack Clocking for Fracturability across 16 Streams or Channels

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