F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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6.22. Dynamic Reconfiguration Avalon MM Timeout

Table 37.   dyn_rcfg_dr_avmm_timeout_reg
Offset 0x54
Addressing Mode 32-bits
Description Dynamic reconfiguration control and status register.
Table 38.   dyn_rcfg_dr_avmm_timeout_reg Field Description
Bit Type Reset Description
31:18 RO 0 Reserved
27:8 RW AVMM_TIMEOUT_RSTVAL=20 Avalon® Memory-Mapped Interface (Avalon MM) Time-Out Tick

Modify the time-out value of an Avalon MM access cycle targeting DR CSR address space or targeting Tile CSR address space through the IP access path.

The time-out resolution is in 256 DR CSR clock ticks. For example, if the CSR clock is 100MHz, a time-out value of 4 represents 4*256*10 ns = 10.24 us.
  • 0 = Disable time-out
  • 1 = 1 * 256 clock ticks
  • 2 = 2 * 256 clock ticks
  • ...
  • N = N * 256 clock ticks.

Do not program this field when Ready For Next Trigger is set to 0.

7:0 RO 0 Reserved
Note: The AVMM_TIMEOUT_RSTVAL must cater for the highest supported frequency such that the reset value of at least 10 us.

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