F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status

Table 55.   dyn_rcfg_dr_rx_reset_initial_reg
Offset 0x78
Addressing Mode 32-bits
Description Dynamic reconfiguration status register.
Table 56.   dyn_rcfg_dr_rx_reset_initial_reg Field Description
Bit Type Reset Description
31:20 RO 0 Reserved
19:0 RO 0 RX Channel Reset Control Initialized Status

RX reset control initialized status[N] = i_rx_lane_current_state[(19-N)*3+2] , where N is the number of channels from 0 to 19.

  • N = 0-3: FHT channels 0-3
  • N = 4-19: FGT channels 0-15