F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023

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2.3. Avalon® Memory-Mapped Interface

Table 8.   Avalon® Memory-Mapped Interface SignalsAll interface signals are clocked by the i_csr_clk clock.
Port Name Width (in bits) I/O Direction Description
i_dr_host_avmm_address 10 Input Address
i_dr_host_avmm_write 1 Input Write command
i_dr_host_avmm_writedata 32 Input Write data
i_dr_host_avmm_read 1 Input Read command
i_dr_host_avmm_readdata 32 Output Read data
i_dr_host_avmm_readdata_valid 1 Output Read data valid
i_dr_host_avmm_waitrequest 1 Output Avalon® memory-mapped interface stall signal for the operation