F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

ID 711009
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: qko1637174220091

Ixiasoft

Document Table of Contents

2.1. Clock Signals

Table 6.  Clock SignalsThe table specifies the required input clocks.
Name Description
i_csr_clk Dynamic Reconfiguration Clock

The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency.

i_cpu_clk NIOS CPU Subsystem Clock
The clock supports the following frequency range:
  • 100 to 250 MHz frequency when Enable ECC protection is disabled.
  • 100 to 200 MHz frequency when Enable ECC protection is enabled.
Note: For simulation, in order to reduce run time, this clock can run at 100 GHz.