The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and the corresponding soft CPU subsystem run on the free-running system clock. The system clock is independent from the transceiver clocks. Dynamically changing the transceiver reference clock does not impact the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and the soft CPU.
- Clock Domain #1: Dynamic reconfiguration ports
- Clock Domain #2: Avalon® memory-mapped interface arbiter (AVMM arbiter) and the dynamic reconfiguration (DR) CSRs
- Clock Domain #3: Soft CPU including the Nios® core
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