F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 4/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

4.2. Dynamic Reconfiguration QSF Settings

This section describes the QSF settings available for dynamic reconfiguration.
When creating the QSF assignments, you must define the <ip_instance_hpath> hierarchy paths for all IPs in use. The .qip file determines the directory of each IP generated by the tool in <ip_name>/ip_name.qip path.
Table 11.  Dynamic Reconfiguration QSF Settings
QSF Settings Description
set_instance_assignment -name IP_TILE_ASSIGNMENT -to <ip_instance_hpath> <tileid> Assign an IP to a specific tile in which you want the IP to be placed.

This assignment is not required if you use "auto-placement" during Quartus Support Logic Generation.

set_instance_assignment -name IP_BB_LOCATION -to <bb_instance_hpath> <bb-location>

Assign a building block instance in the design to a specific location in the tile to which the IP containing the building block is assigned.

Note that this assignment does not identify a specific tile.

This assignment is not required if you use "auto-placement" during Quartus Support Logic Generation.

set_instance_assignment -name IP_RECONFIG_GROUP -to <ip_instance_hpath> <reconfig-group-id-string> Assign a Tile IP compliant IP in design to a named reconfiguration group. All IP in a group are located in the same tile.
set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE -to <ip_instance_hpath> ON|OFF Indicate if a Tile IP compliant IP instance is active at startup; also supplies the clocks.
set_instance_assignment -name IP_RECONFIG_ID -to <ip_instance_hpath> <positive-number-greater-than-zero> Specify a positive integer > 0 as an identifier for an IP. All such identifiers should be consecutive. The IDs are global, i.e. across the entire design. The reconfiguration IDs are defined globally and must be unique per Quartus design but not per Tile.

The provided ID serves as a base for all subprofiles associated with that IP and the IDs for the subprofiles increment sequentially from the provided ID. If you do not provide an ID, the tool assigns an ID.

If the IP instances require consistent reconfiguration IDs assigned by Quartus per compilation, you should specify the reconfiguration IDs per IP instance. If you do not specify a reconfiguration ID in the qsf file, the Quartus® Prime Pro Edition auto-assigns the reconfiguration IDs. The generated .h file contains the reconfiguration ID value used per DR profile. Refer to Determining Profile Numbers.
Attention: When using this assignment, be careful not to assign reconfiguration IDs that overlap and cause collisions between subprofile IDs. (For example, two subprofiles having the same ID).
set_global_assignment -name IP_RECONFIG_GROUP_TYPE <reconfig-group-id-string>:<exclusive|inclusive>:clk_master
Assign a reconfiguration group type to a Tile IP compliant IP in the design.
  • Not given implies inclusive, exclusive implies not inclusive and vice-versa.

    Exclusive indicates that the group only exists by itself after dynamic reconfiguration. Inclusive indicates that the group can exist simultaneously with other groups after dynamic reconfiguration.

  • clk_master implies that the QSF IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL is available for one and only one building block instance in the group.
set_global_assignment -name IP_RECONFIG_GROUP_PARENT <parent-reconfig-group-id-string>:<child-reconfig-group-id-string> Create group hierarchy, should be cumulative like VERILOG_FILE.
set_instance_assignment -name IP_COLOCATE -from <hpath1> -to <hpath2> F_TILE

A QSF that associates a hub IP like the DR controller, with a slot IP like a protocol IP it is controlling.

The IP instance represented by hpath1 and hpath2 should be put in the same F-tile.

IP_COLOCATE is assigned on a "per IP" basis, not a "per profile" basis.
Note: The hpath1 is the hierarchy path of the Dynamic Reconfiguration Suite IP in your design and hpath2 is the hierarchy path of the Protocol IP in your design.
set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name>

Indicate which bb_m_hdpladadapt_rx or bb_m_hdpldadapt_tx instance supplies the master clock.

The allowed clock port names are:
  • pld_pcs_rx_clk_out1_dcm(to be used for RX Simplex designs)
  • pld_pcs_tx_clk_out1_dcm(to be used for either Duplex or TX Simplex designs)
All IP in the group containing <ip_instance_hpath> and any sub-groups receive this master clock.

QSF assignment example required for the dynamic reconfiguration designs

The Tile Interface Planner derives both the tile locations and IP hierarchy for the IP_TILE_ASSIGNMENT and IP_BB_LOCATION assignments.

The following .qsf assignments illustrate the required settings for a design using the Ethernet Multirate Intel® FPGA IP: 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst|dr_f_0 \
   -to ex_100G_mr_dut|eth_f_dr_0 -entity eth_dr_ed
The following .qsf assignments illustrate the required settings for a design using the CPRI Multirate Intel® FPGA IP: 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_ctrl_inst|dr_f_0 \
   -to GEN_CPRIPHY_MR_INST[0].cpriphy_dr_ed_dut_wrapper|cpriphy_mr_dut|cpriphy_mr_f_0 \
   -entity cpriphy_dr_ed_hw
The following .qsf assignments illustrate the required settings for a design using the PMA/FEC Direct PHY Multirate Intel® FPGA IP: 
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 \
-to dut|directphy_f_dr_0
Note: The additional .qsf settings required for dynamic reconfiguration are contained within the CPRI, Ethernet, and PMA/FEC Direct PHY Multirate Intel® FPGA IPs themselves.
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