Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 7/26/2022

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Document Table of Contents

2.1. Boot Flow Overview for FPGA Configuration First Mode

You can program the Intel Stratix 10 SoC device to configure the FPGA first and then boot the HPS. The available configuration data sources configure the FPGA core and periphery first in this mode. After completion, you may optionally boot the HPS. All of the I/O, including the HPS-allocated I/O, are configured and brought out of tri-state. If the HPS is not booted:
  • The HPS is held in reset.
  • HPS-dedicated I/O are held in reset.
  • HPS-allocated I/O are driven with reset values from the HPS.
If the FPGA is configured before the HPS boots, the boot flow looks like the example figure below. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).
Figure 1. Typical FPGA Configuration First Boot Flow
Table 2.  FPGA Configuration First StagesThe sections following this table describe each stage in more detail.
Time Boot Stage Device State
TPOR to T1 POR Power-on reset
T1 to T2 Secure Device Manager (SDM)- Boot ROM
  1. SDM samples the MSEL pins to determine the configuration scheme and boot source.
  2. SDM establishes the device security level based on eFuse values.
  3. SDM initializes the device by reading the configuration firmware (initial part of the bitstream) from the boot source.
  4. SDM authenticates and decrypts the configuration firmware (this process occurs as necessary throughout the configuration).
  5. SDM starts executing the configuration firmware.
T2 to T3 SDM- configuration firmware
  1. SDM I/O are enabled.
  2. SDM configures the FPGA I/O and core (full configuration) and enables the rest of your configured SDM I/O.
  3. SDM loads the FSBL from the bitstream into HPS on-chip RAM.
  4. SDM enables HPS SDRAM I/O and optionally enables HPS debug.
  5. FPGA is in user mode.
  6. HPS is released from reset. CPU1-CPU3 are in a wait-for-interrupt (WFI) state.
T3 to T4 First-Stage Bootloader (FSBL)
  1. HPS verifies the FPGA is in user mode.
  2. The FSBL initializes the HPS, including the SDRAM.
  3. HPS loads SSBL into SDRAM.
  4. HPS peripheral I/O pin mux and buffers are configured. Clocks, resets, and bridges are also configured.
  5. HPS I/O peripherals are available.
T4 to T5 Second-Stage Bootloader (SSBL)
  1. HPS bootstrap completes.
  2. OS is loaded into SDRAM.
T5 to TBoot_Complete Operating System (OS) The OS boots and applications are scheduled for runtime launch.
Note: The location of the source files for configuration, FSBL, SSBL, and OS can vary and are described in the System Layout for FPGA Configuration First Mode section.