Stratix® 10 Configuration User Guide

ID 683762
Date 4/05/2024
Document Table of Contents

1.1. Stratix® 10 Configuration Overview

All Stratix® 10 FPGAs and SoCs are devices that include a Secure Device Manager (SDM) to manage FPGA configuration and security. The SDM provides a failsafe, strongly authenticated, programmable security mode for device configuration. Previous FPGA families include a fixed state machine to manage device configuration.

The Quartus® Prime software also provides flexible and robust security features to protect sensitive data, intellectual property, and the device itself under both remote and physical attacks. Configuration bitstream authentication ensures that the firmware and configuration bitstream are from a trusted source. Encryption prevents theft of intellectual property. The Quartus® Prime software also compresses FPGA bitstreams, reducing memory utilization such as the on-board quad SPI flash device that is storing the FPGA bitstreams.

Intel describes configuration schemes from the point of view of the FPGA. Stratix® 10 devices support active and passive configuration schemes. In active configuration schemes the FPGA acts as the master and the external memory acts as a slave device. In passive configuration schemes an external host acts as the master and controls configuration. The FPGA acts as the slave device. All Stratix® 10 configuration schemes support design security and partial reconfiguration. All Stratix® 10 active configuration schemes support remote system update (RSU) with quad SPI flash memory. To implement RSU in passive configuration schemes, an external controller must store and drive the configuration bitstream.

Stratix® 10 devices support the following configuration schemes:

  • Avalon® streaming ( Avalon® -ST)
  • JTAG
  • Configuration via Protocol (CvP)
  • Active Serial (AS) normal and fast modes
Table 1.   Stratix® 10 Devices Configuration Scheme, Data Width, and MSEL
Configuration Scheme Data Width (bits) MSEL[2:0]
Passive Avalon® -ST 321 000
161 101
8 110
JTAG 1 111
Configuration via Protocol (CvP) x1, x2, x4, x8, x16 lanes

001 2

Active AS - fast mode 41


AS - normal mode 41 011


The Avalon® -ST configuration scheme is a passive configuration scheme. Avalon® -ST is the fastest configuration scheme for Stratix® 10 devices. Avalon® -ST configuration supports x8, x16, and x32 modes. The x16 and x32 bit modes use general-purpose I/Os (GPIOs) for configuration. The x8 bit mode uses dedicated SDM I/O pins.

Note: The AVST_data[15:0], AVST_data[31:0], AVST_clk, and AVST_valid use dual-purpose GPIOs. You can use these pins as regular I/Os after the device enters user mode.

Avalon® -ST supports backpressure using the AVST_READY and AVST_VALID pins. Because the time to process the incoming bitstream varies, backpressure support is necessary to transfer data to the Stratix® 10 device. For more information about the Avalon® -ST refer to the Avalon® Interface Specifications.


You can configure the Stratix® 10 device using the dedicated JTAG pins. The JTAG port provides seamless access to many useful tools and functions. In addition to configuring the Stratix® 10, you use the JTAG port for debugging with Signal Tap or the System Console tools.

The JTAG port has the highest priority and overrides the MSEL pin settings. Consequently, you can configure the Stratix® 10 device over JTAG even if the MSEL pins specify a different configuration scheme unless you disabled JTAG for security reasons.


CvP uses an external PCIe* host device as a Root Port to configure the Stratix® 10 device over the PCIe* link. You can specify up to a x16 PCIe* link. Stratix® 10 devices support two CvP modes, CvP initialization and CvP update.
Note: Typically, the data rate of the device's internal configuration data path, not the PCIe* link width, limits the configuration data rate. The maximum data rate depends on the PCIe* generation and number of lanes.
CvP initialization process includes the following two steps:
  1. During the board power up, the CvP uses quad SPI memory in AS x4 mode to configure the FPGA with the periphery image to enable CvP interface that includes the PCIe* IP. The PCIe* link training establishes the PCIe* link of the CvP PCIe* IP before the core fabric configures.
  2. The host device uses the CvP PCIe* link to configure your design in the core fabric.

CvP update mode updates the FPGA core image using the PCIe* link already established from a previous full chip configuration or CvP initialization configuration. After the Stratix® 10 enters user mode, you can use the CvP update mode to reconfigure the FPGA fabric. This mode has the following advantages:

  • Allows to change core algorithms logic blocks.
  • Provides a mechanism for standard updates as a part of a release process.
  • Customizes core processing for different components that are part of a complex system.

For Stratix® 10 SoC devices, CvP is only supported in FPGA configuration first mode.

For more information refer to the Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide.

AS Normal Mode

Active Serial x4 or AS x4 or Quad SPI is an active configuration scheme that supports flash memories capable of three- and four-byte addressing. Upon power up, the SDM boots from a boot ROM which uses three-byte addressing to load the configuration firmware from the Quad SPI flash. After the configuration firmware loads, the Quad SPI flash operates using four-byte addressing for the rest of the configuration process. This mode supports the following third-party flash devices:

  • Micron* MT25QU128, MT25QU256, MT25QU512, MT25QU01G, MT25QU02G
  • Macronix* MX25U128, MX25U256, MX25U512, MX66U512, MX66U1G, MX66U2G

Refer to the Supported Flash Devices for Stratix® 10 Devices for complete list of supported flash devices.

AS Fast Mode

The only difference between AS normal mode and fast mode is that this mode does not delay for 10 ms before beginning configuration. Use this mode to meet the link up requirement for PCIe* or for other systems with strict timing requirements.

In AS fast mode, the power-on sequence must ensure that the quad SPI flash memory is out of reset before the SDM because the Stratix® 10 device accesses flash memory immediately after exiting reset. The power supply must be able to provide an equally fast ramp up for the Stratix® 10 device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to report that the memory is missing. Consequently, configuration fails.

Refer to the Stratix® 10 Device Family Pin Connection Guidelines and AN692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, and Stratix® 10 Devices for additional details.

1 This configuration scheme is not supported for Stratix® 10 GX 10M devices.
2 Before you can configure the core image using CvP, you must configure either the periphery image or the full image configuration via the AS scheme. The CvP core image is loaded by the host via PCIe link, which is referred to as passive.